NXP Semiconductors K32 L2A Series, Reference Manual, Page: 754 / 1379

28.3.7 Clear Timer Enable Register (LPITx_CLRTEN)
Address: 4003_0000h base + 18h offset = 4003_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0 0 0 0
W
CLR_T_EN_3 CLR_T_EN_2 CLR_T_EN_1 CLR_T_EN_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_CLRTEN field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
CLR_T_EN_3
Clear Timer 3 Enable
Writing a '1' to this bit will disable the timer channel 3. This bit can be used in addition to T_EN bit in
TCTRL3 register. Writing a 1 will not enable the counter. This bit is self clearing and will always read 0.
0 No Action
1 Clear T_EN bit for Timer Channel 3
2
CLR_T_EN_2
Clear Timer 2 Enable
Writing a '1' to this bit will disable the timer channel 2. This bit can be used in addition to T_EN bit in
TCTRL2 register. Writing a 1 will not enable the counter. This bit is self clearing and will always read 0.
0 No Action
1 Clear T_EN bit for Timer Channel 2
1
CLR_T_EN_1
Clear Timer 1 Enable
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
754 NXP Semiconductors