NXP Semiconductors K32 L2A Series, Reference Manual, Page: 749 / 1379

LPITx_PARAM field descriptions (continued)
Field Description
Number of timer channels implemented.
28.3.3 Module Control Register (LPITx_MCR)
Address: 4003_0000h base + 8h offset = 4003_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DBG_EN
DOZE_EN
SW_
RST
M_CEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_MCR field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
DBG_EN
Debug Enable Bit
Allows the timer channels to be stopped when the device enters the Debug mode
0 Timer channels are stopped in Debug mode
1 Timer channels continue to run in Debug mode
2
DOZE_EN
DOZE Mode Enable Bit
Allows the timer channels to be stopped or continue to run when the device enters the DOZE mode
0 Timer channels are stopped in DOZE mode
1 Timer channels continue to run in DOZE mode
1
SW_RST
Software Reset Bit
Resets all channels and registers, except the Module Control Register. Remains set until cleared by
software.
0 Timer channels and registers are not reset
1 Timer channels and registers are reset
0
M_CEN
Module Clock Enable
Table continues on the next page...
Chapter 28 Low Power Interrupt Timer (LPIT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 749