NXP Semiconductors K32 L2A Series, Reference Manual, Page: 715 / 1379

27.2.14 Master FIFO Control Register (LPI2Cx_MFCR)
Address: Base a 58h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RXWATER
0
TXWATER
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPI2Cx_MFCR field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
RXWATER
Receive FIFO Watermark
The Receive Data Flag is set whenever the number of words in the receive FIFO is greater than
RXWATER. Writing a value equal or greater than the FIFO size will be truncated.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
TXWATER Transmit FIFO Watermark
The Transmit Data Flag is set whenever the number of words in the transmit FIFO is equal or less than
TXWATER. Writing a value equal or greater than the FIFO size will be truncated.
27.2.15 Master FIFO Status Register (LPI2Cx_MFSR)
Address: Base a 5Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 RXCOUNT 0 TXCOUNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPI2Cx_MFSR field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
RXCOUNT
Receive FIFO Count
Returns the number of words in the receive FIFO.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
TXCOUNT Transmit FIFO Count
Returns the number of words in the transmit FIFO.
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 715