NXP Semiconductors K32 L2A Series, Reference Manual, Page: 712 / 1379

27.2.10 Master Configuration Register 3 (LPI2Cx_MCFGR3)
The MCFGR3 should only be written when the I2C Master is disabled.
Address: Base a 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PINLOW
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPI2Cx_MCFGR3 field descriptions
Field Description
31–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–8
PINLOW
Pin Low Timeout
Configures the pin low timeout flag in clock cycles. If SCL and/or SDA is low for longer than (PINLOW *
256) cycles then PLTF is set. When set to zero, this feature is disabled.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
27.2.11 Master Data Match Register (LPI2Cx_MDMR)
Address: Base a 40h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MATCH1
0
MATCH0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPI2Cx_MDMR field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
MATCH1
Match 1 Value
Compared against the received data when receive data match is enabled.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
MATCH0 Match 0 Value
Compared against the received data when receive data match is enabled.
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
712 NXP Semiconductors