NXP Semiconductors K32 L2A Series, Reference Manual, Page: 711 / 1379

LPI2Cx_MCFGR1 field descriptions (continued)
Field Description
110 Divide by 64.
111 Divide by 128.
27.2.9 Master Configuration Register 2 (LPI2Cx_MCFGR2)
The MCFGR2 should only be written when the I2C Master is disabled.
Address: Base a 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FILTSDA
0
FILTSCL
0
BUSIDLE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPI2Cx_MCFGR2 field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
FILTSDA
Glitch Filter SDA
Configures the I2C master digital glitch filters for SDA input, a configuration of 0 will disable the glitch filter.
Glitches equal to or less than FILTSDA cycles long will be filtered out and ignored. The latency through
the glitch filter is equal to FILTSDA cycles and must be configured less than the minimum SCL low or high
period.
The glitch filter cycle count is not affected by the PRESCALE configuration and is automatically bypassed
in High Speed mode.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
FILTSCL
Glitch Filter SCL
Configures the I2C master digital glitch filters for SCL input, a configuration of 0 will disable the glitch filter.
Glitches equal to or less than FILTSCL cycles long will be filtered out and ignored. The latency through the
glitch filter is equal to FILTSCL cycles and must be configured less than the minimum SCL low or high
period.
The glitch filter cycle count is not affected by the PRESCALE configuration and is automatically bypassed
in High Speed mode.
15–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
BUSIDLE Bus Idle Timeout
Configures the bus idle timeout period in clock cycles. If both SCL and SDA are high for longer than
BUSIDLE cycles, then the I2C bus is assumed to be idle and the master can generate a START condition.
When set to zero, this feature is disabled.
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 711