NXP Semiconductors K32 L2A Series, Reference Manual, Page: 70 / 1379

ADC channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
10100 AD20 Reserved ADC0_SE20
10101 AD21 Reserved ADC0_SE21
10110 AD22 Reserved ADC0_SE22
10111 AD23 Reserved 12-bit DAC0 Output/
ADC0_SE23
11000 AD24 Reserved Reserved
11001 AD25 Reserved Reserved
11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)
11011 AD27 Bandgap (Diff)
2
Bandgap (S.E)
2
11100 AD28 Reserved Reserved
11101 AD29 -VREFH (Diff) VREFH (S.E)
11110 AD30 Reserved VREFL
11111 AD31 Module Disabled Module Disabled
1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
for details.
2. This is the PMC bandgap 1V reference voltage. Prior to reading from this ADC channel, ensure that you enable the
bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (V
BG
)
specification.
3.7.1.4 ADC analog supply and reference connections
See Analog reference options .
• This device includes dedicated VDDA and VSSA pins.
• This device contains dedicated VREFH and VREFL pins in all packages.
• The output of the on-chip high precision VREF module is shared with VREFH.
When VREF is enabled, this pin needs to connect a capacitor to ground.
The ADC supports the following references:
• VREFH is connected to VREF_OUT as the external reference.
• VDDA is connected as the V
ALTH
reference.
3.7.1.5 ADC clock source
The ADC module clock is sourced from the Peripheral Clock Control (PCC) module.
3.7.2 CMP configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Analog
K32 L2A Reference Manual, Rev. 2, 01/2020
70 NXP Semiconductors