NXP Semiconductors K32 L2A Series, Reference Manual, Page: 330 / 1379

15.6 Functional description
This section discusses the programming model and operation of the CAU.
15.6.1 CAU programming model
The 4-entry FIFO is indirectly mapped into a 4-KB address space associated with the
CAU located on this device. This address space is effectively split into two equal regions:
• one used to directly write commands for CAU load operations
• the other used to send commands and input operands for CAU loads
Data writes on the PPB are loaded into this FIFO and automatically converted into CAU
load operands by the CAU translator. Data reads on the PPB are converted into CAU
store register operations where the result is returned to the processor as the read data
value.
The CAU requires a 15-bit command, and optionally, a 32-bit input operand, for each
CAU load, PPB write. The 15-bit command includes the 9-bit opcode and other bits
statically formed by the CAU translator logic controlling the CAU.
The following figure shows the 4-KB address space and the mapping of the CAU
commands in this space.
NOTE
• Although the indirect store/load portion of the address
space in the figure below shows only the indirect load/store
commands, direct load commands can also be used in this
space. However, it is more efficient to use the direct load
portion of the address space.
• Accesses to the reserved space in the direct load space are
terminated with an error, while accesses to the reserved
space in the indirect load/store space are detected as an
illegal CAU command. See
CAU integrity checks for
details.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
330 NXP Semiconductors