NXP Semiconductors K32 L2A Series, Reference Manual, Page: 332 / 1379

15.6.1.2 Indirect loads
For CAU load operations requiring a 32-bit input operand, the address contains the 9-bit
opcode to be passed to the CAU while the data is the 32-bit operand. Specifically, the
CAU address and data for these indirect writes is shown in the figure below.
CAU base address
1 0 0
31 0 4 8 12 16 20 24 28
CAU_CMD Write address
Op1
31 0 4 8 12 16 20 24 28
Write data
Figure 15-5. Indirect loads
15.6.1.3 Indirect stores
For CAU store operations, a PPB read is performed with the appropriate CAU store
register opcode embedded in the address. This appears as another indirect command. The
detail of Indirect stores is shown in the figure below.
CAU base address 1 0 0
31 0 4 8 12 16 20 24 28
Rn
Read address
CAx
31 0 4 8 12 16 20 24 28
Read data
Figure 15-6. Indirect store
15.6.2 CAU integrity checks
If an illegal operation or access is attempted, the PPB bus cycle is terminated with an
error response and the operation is aborted and not sent to the CAU.
The CAU performs a series of address and data integrity checks as described in the
following sections. The results of these checks are logically summed together and, if
appropriate, a PPB error termination is generated.
15.6.2.1 Address integrity checks
The CAU address checking includes the following. See Figure 15-3 for the CAU memory
map details.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
332 NXP Semiconductors