NXP Semiconductors K32 L2A Series, Reference Manual, Page: 248 / 1379

Table 14-1. Kinetis Bootloader Peripheral Pinmux (continued)
Peripheral Instance Alt Mode Pins
PTD6, SPI1_MOSI
PTD7, SPI1_MISO
2
1
2 PTB20, SPI2_PCS0
PTB21, SPI2_SCK
PTB22, SPI2_MOSI
PTB23, SPI2_MISO
USB 0 0 USB0_DP
USB0_DM
1. SPI instances 0 and 2 are only available on 100 LQFP packages.
14.1.2 Bootloader Memory Access
While executing, the Kinetis Bootloader uses the following address ranges in ROM and
RAM memory:
• 0x1C00_0000 – 0x1C00_7FFF (ROM)
• 0x1FFF_A000 – 0x1FFF_B5C7 (RAM)
14.2 Introduction
The Kinetis bootloader is the program residing in the on-chip read-only memory (ROM)
of a Kinetis microcontroller device. There is hardware logic in place at boot time that
either starts execution of an embedded image available on the internal flash memory, or
starts the execution of the Kinetis Bootloader from on-chip ROM.
The Kinetis Bootloader’s main task is to provision the internal flash memory with an
embedded firmware image during manufacturing, or at any time during the life of the
Kinetis device. The Kinetis Bootloader does the provisioning by acting as a slave device,
and listening to various peripheral ports where a master can start communication.
For the Kinetis device, the Kinetis Bootloader can interface with USB, LPI2C, LPSPI,
and LPUART peripherals in slave mode and respond to the commands sent by a master
(or host) communicating on one of those ports. The host/master can be a firmware-
download application running on a PC or an embedded host communicating with the
Kinetis Bootloader. Regardless of the host/master (PC or embedded host), the Kinetis
Bootloader always uses a command protocol to communicate with that host/master.
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
248 NXP Semiconductors