NXP Semiconductors K32 L2A Series, Reference Manual, Page: 232 / 1379

x CYCLE RULER
hclk
BME AHB Input Bus
mx_haddr
mx_hattr
mx_hwrite
mx_hwdata
mx_hrdata
mx_hready
BME AHB Output Bus
sx_haddr
sx_hattr
sx_hwrite
sx_hwdata
sx_hrdata
sx_hready
BME Datapath
control_state_dp1
control_state_dp2
reg_addr_data_dp
x+3
x+2 x+1
next
next
next
next
next
next
5..v_wxyz
5..v_wxyz wdata bfi rdata
wdata bfi rdata
rdata
400v_wxyz
400v_wxyz
wdata
Figure 13-1. Decorated store: bit field insert timing diagram
All the decorated store operations follow the same execution template shown in Figure
13-1 , a two-cycle read-modify-write operation:
1. Cycle x, 1st AHB address phase: Write from input bus is translated into a read
operation on the output bus using the actual memory address (with the decoration
removed) and then captured in a register.
2. Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual)
memory address is output
3. Cycle x+1, 1st AHB data phase: Memory read data is modified using the input bus
write data and the function defined by the decoration and captured in a data register;
the input bus cycle is stalled.
4. Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the output
write data bus.
NOTE
Any wait states inserted by the slave device are simply passed
through the BME back to the master input bus, stalling the
AHB transaction cycle for cycle.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
232 NXP Semiconductors