NXP Semiconductors K32 L2A Series, Reference Manual, Page: 153 / 1379

Table 9-4. MDM-AP Control register assignments (continued)
Bit Name Secure
1
Description
If the core is in a Stop or Wait mode, then Debug Request bit can be
used to wake the core and transition to a halted state.
3 System Reset Request Y Set to force a system reset. The system remains held in reset until
System Reset Request bit is cleared.
4 Core Hold Reset N Configuration bit to control core operation at the end of system reset
sequencing.
0 Normal operation: At the end of system reset sequencing, release
the core from reset (along with the rest of the system).
1 Suspend operation: At the end of reset sequencing, hold the core in
reset. After the system enters this suspended state, clearing this
control bit immediately releases the core from reset and CPU operation
begins.
5 VLLSx Debug Request
(VLLDBGREQ) N Set to configure the system to be held in reset after the next recovery
from a VLLSx mode. VLLSx Debug Request bit is ignored on a VLLS
wakeup via the Reset pin. During a VLLS wakeup via the Reset pin,
the system can be held in reset by holding the reset pin asserted,
allowing the debugger to reinitialize the debug modules.
VLLSx Debug Request bit holds the system in reset when VLLSx
modes are exited, to allow the debugger time to re-initialize debug IP
before the debug session continues.
The Mode Controller captures VLLSx Debug Request bit logic on entry
to VLLSx modes. Upon exit from VLLSx modes, the Mode Controller
will hold the system in reset until VLLDBGACK is asserted.
VLLDBGREQ clears automatically due to the POR reset generated as
part of the VLLSx recovery.
6 VLLSx Debug Acknowledge
(VLLDBGACK) N Set to release a system being held in reset following a VLLSx recovery
VLLSx Debug Acknowledge bit is used by the debugger to release the
system reset when it is being held on VLLSx mode exit. The debugger
re-initializes all debug IP and then asserts VLLSx Debug Acknowledge
bit to allow the Mode Controller to release the system from reset and
allow CPU operation to begin.
VLLDBGACK is cleared by the debugger or can be left set, because it
clears automatically due to the POR reset generated as part of the
next VLLSx recovery.
7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge that the DAP LLS and VLLS Status bits
have been read. This acknowledge automatically clears the status bits.
This bit is used by the debugger to clear the sticky LLS and VLLSx
mode entry status bits. This bit is asserted and cleared by the
debugger.
8–
31 Reserved for future use N
1. Command available in secure mode
Chapter 9 Debug
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 153