NXP Semiconductors K32 L2A Series, Reference Manual, Page: 152 / 1379

DPACC
APSEL
Decode
Core 0
Data[31:0] A[3:2] RnW
APACC
Data[31:0] A[3:2] RnW
Deb
ug P
or
t ID R
egist
er (IDCODE)
AP Select (SELECT)
C
ontr
ol/St
atus (CTRL/S
TA
T)
R
ead Buf
fer (RDB
UFF)
0x00 0x04 0x08 0x0C
DP Registers
Data[31:0] A[7:4] RnW A[3:2]
AHB Access
Port
(AHB-AP)
St
atus
C
ontr
ol
IDR
0x00 0x0
1
0x3F
MDM-AP
Generic
Debug Port
(DP)
See Control and Status
Register Descriptions
Via SWD (if the debugger tools
can interface to the CPU)
The MDM-AP can support:
-Basic run/halt control
-2 breakpoints
-2 watchpoints
MDM-AP0 has flash erase capability,
VLLS debug configuration
MDM-AP0 has:
-Debug disable
-Debug request
-Systems reset request
-Core hold reset
Core Debug
Figure 9-2. MDM AP addressing
9.4.1 MDM-AP Control Register
Table 9-4. MDM-AP Control register assignments
Bit Name Secure
1
Description
0 Flash Mass Erase in Progress Y Set to cause mass erase. Cleared by a Power-On Reset (POR).
When mass erase is disabled (via MEEN), the erase request does not
occur and the Flash Mass Erase in Progress bit continues to assert
until the next system reset.
NOTE: When the reset pin has been disabled and security has been
enabled by means of the FSEC register, a mass erase can be
performed only by setting both the mass erase and system
reset request bits in the MDM-AP register.
1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set, it
overrides the C_DEBUGEN bit within the DHCSR and force disables
Debug logic.
2 Debug Request N Set to force the core to halt.
Table continues on the next page...
SWD status and control registers
K32 L2A Reference Manual, Rev. 2, 01/2020
152 NXP Semiconductors