NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1368 / 1379

Table 54-1. Watchdog timeout availability
Reference clock Prescaler Watchdog time-out availability
Internal LPO_CLK
Pass through
~1 ms–65.5 s (if LPO_CLK = 1 kHz); (~1 ms–65.5 s)/128 (if
LPO_CLK = 128 kHz).
1
÷256
~256 ms–16,777.2 s (if LPO_CLK = 1 kHz); ~2 ms–131.1 s (if
LPO_CLK = 128 kHz).
Internal 8 MHz (SIRC)
Pass through 125 ns–8.1925 ms
÷256 32 µs–2.09728 s
1 MHz (from bus or external)
Pass through 1 µs–65.54 ms
÷256 256 µs–16.777 s
20 MHz (from bus or external)
Pass through 50 ns–3.277 ms
÷256 12.8 µs–838.8 ms
1. The default timeout value after reset is approximately 1 s (if LPO_CLK = 1 kHz), or 1/128 s (if LPO_CLK = 128 kHz).
NOTE
When the programmer switches clock sources during
reconfiguration, the watchdog hardware holds the counter at
zero for 2.5 periods of the previous clock source and 2.5
periods of the new clock source after the configuration time
period (128 bus clocks) ends. This delay ensures a smooth
transition before restarting the counter with the new
configuration.
54.3.4 Using interrupts to delay resets
• When interrupts are enabled (CS[INT] = 1): After a reset-triggering event (like a
counter timeout or invalid refresh attempt), the watchdog first generates an interrupt
request. Next, the watchdog delays 128 bus clocks (from the interrupt vector fetch,
not the reset-triggering event) before forcing a reset, to allow the interrupt service
routine (ISR) to perform tasks (like analyzing the stack to debug code).
• When interrupts are disabled (CS[INT] = 0): the watchdog does not delay the
forcing a reset.
54.3.5 Backup reset
NOTE
A clock source other than the bus clock must be used as the
reference clock for the counter; otherwise, the backup reset
function is not available.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1368 NXP Semiconductors