NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1359 / 1379

54.2 Memory map and register definition
WDOG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_6000 Watchdog Control and Status Register (WDOG0_CS) 32 R/W See section 54.2.1/1359
4007_6004 Watchdog Counter Register (WDOG0_CNT) 32 R/W 0000_0002h 54.2.2/1361
4007_6008 Watchdog Timeout Value Register (WDOG0_TOVAL) 32 R/W 0000_0400h 54.2.3/1362
4007_600C Watchdog Window Register (WDOG0_WIN) 32 R/W 0000_0000h 54.2.4/1363
54.2.1 Watchdog Control and Status Register (WDOGx_CS)
This section describes the function of Watchdog Control and Status Register.
NOTE
TST is cleared (0:0) on POR only. Any other reset does not
affect the value of this field.
Address: 4007_6000h base + 0h offset = 4007_6000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WIN
FLG
CMD32EN
PRES
0
CLK EN INT
UPDATE
TST DBG WAIT STOP
W
w1c
Reset
0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0
Chapter 54 Watchdog timer (WDOG32)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1359