NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1222 / 1379

48.1.3.3.5.2 Function
The TRNG0 Poker Maximum Limit Register defines Maximum Limit allowable during
the TRNG Statistical Check Poker Test. Note that this offset (0x0C) is used as
TRNG0_PKRMAX only if TRNG0_MCTL[PRGM] is 1. If TRNG0_MCTL[PRGM] is
0, this offset is used as the TRNG0_PKRSQ readback register.
48.1.3.3.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved PKR_MAX
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PKR_MAX
W
Reset
0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0
48.1.3.3.5.4 Fields
Field Function
31-24
—
23-0
PKR_MAX
Poker Maximum Limit.
During the TRNG Statistical Checks, a "Poker Test" is run which requires a maximum and minimum limit.
The maximum allowable result is programmed in the TRNG0_PKRMAX[PKR_MAX] register. This field is
writable only if TRNG0_MCTL[PRGM] bit is 1. This register is cleared to the default POR value by writing
the TRNG0_MCTL[RST_DEF] bit to 1. Note that the TRNG0_PKRMAX and TRNG0_PKRRNG registers
combined are used to define the minimum allowable Poker result, which is PKR_MAX - P 1.
Note that if TRNG0_MCTL[PRGM] bit is 0, this register address is used to read the Poker Test Square
Calculation result in register TRNG0_PKRSQ, as defined in the following section.
48.1.3.3.6 TRNG0 Poker Square Calculation Result (TRNG0_PKRSQ)
48.1.3.3.6.1 Address
Register Offset Description
TRNG0_PKRSQ 400A500Ch Accessible at this address when
TRNG0_MCTL[PRGM] = 0]
Standalone True Random Number Generator (SA-TRNG).
K32 L2A Reference Manual, Rev. 2, 01/2020
1222 NXP Semiconductors