NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1105 / 1379

43.2.9 Peripheral Clock Status Register (SIM_PCSR)
The System Clock Generator will provide a 'ready' status for all peripheral clock sources.
The 'ready' status bits of the respective peripheral clock source can be polled by software
prior to choosing a clock as the source clock for a peripheral.
Address: 4007_4000h base + 10ECh offset = 4007_50ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_PCSR field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
CS7
Clock Source 7
Clock Source 7 (Peripheral PLL) Status
0 Clock not ready.
1 Clock ready.
6
CS6
Clock Source 6
Clock Source 6 (System PLL) Status
0 Clock not ready.
1 Clock ready.
5
CS5
Clock Source 5
Clock Source 5 (System FLL) Status
0 Clock not ready.
1 Clock ready.
4
CS4
Clock Source 4
Clock Source 4 (RTC Oscillator) Status
0 Clock not ready.
1 Clock ready.
3
CS3
Clock Source 3
Table continues on the next page...
Chapter 43 System Integration Module (SIM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1105