NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1082 / 1379

42.2.17 Fast IRC Trim Configuration Register (SCG_FIRCTCFG)
The FIRCTCFG register cannot be changed when Fast IRC tuning is enabled. When the
Fast IRC tuning is enabled, writes to this register are ignored, and there is no transfer
error.
Address: 4007_B000h base + 30Ch offset = 4007_B30Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TRIMDIV
0
TRIMSRC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_FIRCTCFG field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
TRIMDIV
Fast IRC Trim Predivide
Divide the System OSC down for Fast IRC trimming.
000 Divide by 1
001 Divide by 128
010 Divide by 256
011 Divide by 512
100 Divide by 1024
101 Divide by 2048
110 Reserved. Writing this value will result in Divide by 1.
111 Reserved. Writing this value will result in a Divide by 1.
7–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
TRIMSRC Trim Source
Configures the external clock source to tune the Fast IRC. TRMSRC must be configured before
programming FIRCSTAT register for trim update
00 USB0 Start of Frame (1 kHz)
01 Reserved
10 System OSC
11 Reserved
Memory Map/Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1082 NXP Semiconductors