NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1071 / 1379

SCG_SOSCCSR field descriptions (continued)
Field Description
0
SOSCEN
System OSC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
0 System OSC is disabled
1 System OSC is enabled
42.2.9 System OSC Divide Register (SCG_SOSCDIV)
The SCG_SOSCDIV register provides the control of 3 clock trees which can be used to
provide optional peripheral functional clocks, or alternative module clocks. Each clock
tree has optional dividers of the input SOSC clock. Changes to SOSCDIV should be done
when System OSC is disabled to prevent glitches to output divided clock.
Address: 4007_B000h base + 104h offset = 4007_B104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SOSCDIV3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SOSCDIV2
0
SOSCDIV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SOSCDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
SOSCDIV3
System OSC Clock Divide 3
Clock divider 3 for System OSC. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 42 System Clock Generator (SCG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1071