NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1022 / 1379

39.2.5 Mode Register (RCM_MR)
This register includes status flags to indicate the state of the mode pins during the last
Chip Reset.
Address: 4007_F000h base + 10h offset = 4007_F010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 BOOTROM 0
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 * * 0
* Notes:
BOOTROM field: The reset state of this register depends on the boot mode. •
RCM_MR field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2–1
BOOTROM
Boot ROM Configuration
Indicates the boot source, the boot source remains set until the next System Reset or software can write
logic one to clear the corresponding mode bit.
While either bit is set, the NMI input is disabled and the vector table is relocated to the ROM base address
at $1C00_0000. These bits should be cleared by writing logic one before executing any code from either
Flash or SRAM.
00 Boot from Flash
01 Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin
10 Boot form ROM due to FOPT[7] configuration
11 Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Reset memory map and register descriptions
K32 L2A Reference Manual, Rev. 2, 01/2020
1022 NXP Semiconductors