NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1021 / 1379

Address: 4007_F000h base + Ch offset = 4007_F00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RSTFLTSEL
0
RSTFLTSS
RSTFLTSR
W
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCM_RPC field descriptions
Field Description
31–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12–8
RSTFLTSEL
Reset Pin Filter Bus Clock Select
Selects the reset pin bus clock filter width:
• Transition lengths less than RSTFLTSEL cycles are filtered.
• Transition lengths between RSTFLTSEL and (RS1) cycles (inclusive) may be filtered.
• Transition lengths greater than (RS1) cycles are not filtered.
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
RSTFLTSS
Reset Pin Filter Select in Stop Mode
Selects how the reset pin filter is enabled in any stop mode. On exit from VLLS mode, this bit should be
reconfigured before clearing PMC_REGSC[ACKISO].
0 All filtering disabled
1 LPO clock filter enabled
RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes
Selects how the reset pin filter is enabled in run and wait modes.
00 All filtering disabled
01 Bus clock filter enabled for normal operation
10 LPO clock filter enabled for normal operation
11 Reserved
Chapter 39 Reset Control Module (RCM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1021