NXP Semiconductors K22F series, Reference Manual, Page: 614 / 1407

28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)
The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are
numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x
denotes the way, y denotes the set, and U and L represent upper and lower word,
respectively. This section represents data for the lower word (bits [31:0]) of all sets in the
indicated way.
Address: 4001_F000h base + 2C4h (8d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[31:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW3SnL field descriptions
Field Description
data[31:0] Bits [31:0] of data entry
28.5 Functional description
The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides
managing the interface between the device and the flash memory, the FMC can be used
to restrict access from crossbar switch masters and —for program flash only—to
customize the cache and buffers to provide single-cycle system-clock data-access times.
Whenever a hit occurs for the prefetch speculation buffer, the cache, or the single-entry
buffer, the requested data is transferred within a single system clock.
28.5.1 Default configuration
Upon system reset, the FMC is configured to provide a significant level of buffering for
transfers from the flash memory:
• Crossbar masters 0, 1, 2 have read access to bank 0 and bank 1.
• For bank 0 and bank 1:
• Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2.
• The cache is configured for least recently used (LRU) replacement for all four
ways.
• The cache is configured for data or instruction replacement.
• The single-entry buffer is enabled.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
614 NXP Semiconductors