NXP Semiconductors K22F series, Reference Manual, Page: 1307 / 1407

48.2.1 LPUART Baud Rate Register (LPUARTx_BAUD)
Address: 4002_A000h base + 0h offset = 4002_A000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MAEN1 MAEN2
M10 OSR
TDMAE
0
RDMAE
0
MATCFG
BOTHEDGE
RESYNCDIS
W
Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LBKDIE
RXEDGIE
SBNS SBR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
LPUARTx_BAUD field descriptions
Field Description
31
MAEN1
Match Address Mode Enable 1
0 Normal operation.
1 Enables automatic address matching or data matching mode for MATCH[MA1].
30
MAEN2
Match Address Mode Enable 2
0 Normal operation.
1 Enables automatic address matching or data matching mode for MATCH[MA2].
29
M10
10-bit Mode select
The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when
the transmitter and receiver are both disabled.
0 Receiver and transmitter use 8-bit or 9-bit data characters.
1 Receiver and transmitter use 10-bit data characters.
28–24
OSR
Oversampling Ratio
This field configures the oversampling ratio for the receiver between 4x (00011) and 32x (11111). Writing
an invalid oversampling ratio (for example, a value not between 4x and 32x) will default to an
oversampling ratio of 16 (01111). The OSR field should only be changed when the transmitter and
receiver are both disabled. Note that the oversampling ratio = OSR + 1.
23
TDMAE
Transmitter DMA Enable
TDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to generate a DMA
request.
0 DMA request disabled.
1 DMA request enabled.
Table continues on the next page...
Chapter 48 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1307