NXP Semiconductors K22F series, Reference Manual, Page: 1093 / 1407

43.4.11 Error Interrupt Status register (USBx_ERRSTAT)
Contains enable bits for each of the error sources within the USB Module. Each of these
bits are qualified with their respective error enable bits. All bits of this register are
logically OR'd together and the result placed in the ERROR bit of the ISTAT register.
After an interrupt bit has been set it may only be cleared by writing a one to the
respective interrupt bit. Each bit is set as soon as the error condition is detected.
Therefore, the interrupt does not typically correspond with the end of a token being
processed. This register contains the value of 0x00 after a reset.
Address: 4007_2000h base + 88h offset = 4007_2088h
Bit 7 6 5 4 3 2 1 0
Read BTSERR 0 DMAERR BTOERR DFN8 CRC16 CRC5EOF PIDERR
Write w1c w1c w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 0 0
USBx_ERRSTAT field descriptions
Field Description
7
BTSERR
This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the error.
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
DMAERR
This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given
the bus before it needs to receive or transmit data. If processing a TX transfer this would cause a transmit
data underflow condition. If processing a RX transfer this would cause a receive data overflow condition.
This interrupt is useful when developing device arbitration hardware for the microprocessor and the USB
module to minimize bus request and bus grant latency. This bit is also set if a data packet to or from the
host is larger than the buffer size allocated in the BDT. In this case the data packet is truncated as it is put
in buffer memory.
4
BTOERR
This bit is set when a bus turnaround timeout error occurs. The USB module contains a bus turnaround
timer that keeps track of the amount of time elapsed between the token and data phases of a SETUP or
OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted
from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
3
DFN8
This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data
fields be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
2
CRC16
This bit is set when a data packet is rejected due to a CRC16 error.
1
CRC5EOF
This error interrupt has two functions. When the USB Module is operating in peripheral mode
(HOSTMODEEN=0), this interrupt detects CRC5 errors in the token packets generated by the host. If set
the token packet was rejected due to a CRC5 error.
When the USB Module is operating in host mode (HOSTMODEEN=1), this interrupt detects End Of Frame
(EOF) error conditions. This occurs when the USB Module is transmitting or receiving data and the SOF
counter reaches zero. This interrupt is useful when developing USB packet scheduling software to ensure
that no USB transactions cross the start of the next frame.
0
PIDERR
This bit is set when the PID check field fails.
Chapter 43 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1093