MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor
9-1
Chapter 9
Modem Miscellaneous Functions
9.1
Reset Function
The MC1321x can be placed in one of two reset conditions either through hardware input M_RSTB or by
writing to Reset Register 00.
9.1.1
Input Pin M_RSTB
Asserting input pin M_RSTB low places the transceiver in a complete reset condition (Off Mode and
power down), and the device stays in this reset mode until M_RSTB is released high. After M_RSTB is
released, the transceiver will transition to the Idle Mode within 10-25 milliseconds, causing an ATTN
interrupt request and allowing CLKO to start at 32.768+ kHz (both of which are default conditions).
9.1.2
Software Reset (Writing to Register 00)
Writing to Reset Register 00 causes a reset condition where the digital logic is reset, but the transceiver is
not powered down. The device is forced to the Idle Mode and the SPI registers are all reset and forced to
their default condition although all data in the Packet RAMs is retained. The reset is held as long as CE
remains asserted and is released when CE is negated high.
9.1.3
Reset Indicator Bit (RST_Ind Register 25, Bit 7)
It is useful to determine if the transceiver has powered-up from a reset condition or from a low power state
that was released via the ATTN signal. The reset indicator bit (reset_ind, RST_Ind Register 25, Bit 7) is
cleared during a reset operation but not during a low power mode such as Doze or Hibernate. The reset_ind
bit gets set by the first read of Register 25 after a reset operation and stays set until another reset operation.
When exiting reset, an interrupt is generated by attn_irq, IRQ_Status Register 24, Bit 10, (the default
condition is with the interrupt mask enabled). This same interrupt can be enabled for exiting Hibernate or
Doze via an ATTN assertion. As a result, the reset_ind bit can determine if the power-up condition is from
the reset condition or a Doze or Hibernate condition.
After exiting reset and responding to the attn_irq interrupt, users should read Register 25 which in turn sets
the reset_ind bit. Thereafter, if the transceiver is put into Doze or Hibernate and then later awakened by an
ATTN assertion, the attn_irq interrupt is also used, but the reset_ind is set signifying that the chip was not
reset and does not need re-initialized.
Summary of Contents for freescale semiconductor MC13211
Page 40: ...MC1321x Pins and Connections MC1321x Reference Manual Rev 1 6 2 6 Freescale Semiconductor...
Page 166: ...Modem Modes of Operation MC1321x Reference Manual Rev 1 6 7 22 Freescale Semiconductor...
Page 172: ...Modem Interrupt Description MC1321x Reference Manual Rev 1 6 8 6 Freescale Semiconductor...
Page 186: ...MCU Modes of Operation MC1321x Reference Manual Rev 1 6 10 8 Freescale Semiconductor...
Page 208: ...MCU Memory MC1321x Reference Manual Rev 1 6 11 22 Freescale Semiconductor...
Page 244: ...MCU Parallel Input Output MC1321x Reference Manual Rev 1 6 13 20 Freescale Semiconductor...
Page 288: ...MCU Central Processor Unit CPU MC1321x Reference Manual Rev 1 6 15 20 Freescale Semiconductor...
Page 308: ...MCU Timer PWM TPM Module MC1321x Reference Manual Rev 1 6 17 16 Freescale Semiconductor...
Page 338: ...Inter Integrated Circuit IIC MC1321x Reference Manual Rev 1 6 19 14 Freescale Semiconductor...
Page 372: ...Development Support MC1321x Reference Manual Rev 1 6 21 20 Freescale Semiconductor...
