Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-25
20.3.10 Data Breakpoint and Mask Registers (DBR, DBMR)
DBR specifies data patterns used as part of the trigger into debug mode. DBR bits are masked by setting
corresponding DBMR bits, as defined in TDR.
DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and through the BDM
port using the WRITE_DREG commands.
The DBR supports aligned and misaligned references.
shows the relationships between
processor address, access size, and location within the 32-bit data bus.
Table 20-18. ABLR Field Description
Field
Description
31–0
Address
Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for
specific addresses are programmed into ABLR.
Table 20-19. ABHR Field Description
Field
Description
31–0
Address
High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
DRc[4:0]: 0x0E (DBR)
0x0F (DBMR)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Data (DBR); Mask (DBMR)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-14. Data Breakpoint & Mask Registers (DBR, DBMR)
Table 20-20. DBR Field Descriptions
Field
Description
31–0
Data
Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a
breakpoint trigger.
Table 20-21. DBMR Field Descriptions
Field
Description
31–0
Mask
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger.
0 The corresponding DBR bit is compared to the appropriate bit of the processor’s local data bus
1 The corresponding DBR bit is ignored
