Timer/PWM Module (TPM)
MCF51CN128 Reference Manual, Rev. 6
19-9
Freescale Semiconductor
19.3.2
TPM-Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other half is read. This allows coherent 16-bit reads in big-endian or
little-endian order that makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPMxSC).
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
10
Fixed frequency clock
11
External clock
Table 19-4. Prescale Factor Selection
PS[2:0]
TPM Clock Divided-by
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
7
6
5
4
3
2
1
0
R
TPMxCNT[15:8]
W
Any write to TPMxCNTH clears the 16-bit counter
Reset
0
0
0
0
0
0
0
0
Figure 19-7. TPM Counter Register High (TPMxCNTH)
7
6
5
4
3
2
1
0
R
TPMxCNT[7:0]
W
Any write to TPMxCNTL clears the 16-bit counter
Reset
0
0
0
0
0
0
0
0
Figure 19-8. TPM Counter Register Low (TPMxCNTL)
Table 19-3. TPM Clock Selection (continued)
CLKSB:CLKSA
TPM Clock to Prescaler Input
