Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
17-22
Freescale Semiconductor
17.4.4.1.2
SCL High (SMBus Free) Timeout
The IIC shall assume that the bus is idle, when it has determined that the SMBCLK and SMBDAT signals
are high for at least THIGH:MAX. HIGH timeout can occur in two ways:
1. HIGH timeout detected after a STOP condition appears on the bus.
2. HIGH timeout detected after a START condition, but before a STOP condition appears on the bus.
Any master detecting either scenario can assume the bus is free then SHTF rises. HIGH timeout occurred
in scenario 2 if it ever detects that both conditions are true: BUSY bit is high and SHTF is high.
17.4.4.1.3
CSMBCLK TIMEOUT MEXT
illustrates the definition of the timeout intervals, TLOW:SEXT and TLOW:MEXT. When
master mode, the I2C must not cumulatively extend its clock cycles for a period greater than
TLOW:MEXT within a byte, where each byte is defined as START-to-ACK, ACK-to-ACK, or
ACK-to-STOP. When CSMBCLK TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the
SLTF.
17.4.4.1.4
CSMBCLK TIMEOUT SEXT
A Master is allowed to abort the transaction in progress to any slave that violates the TLOW:SEXT or
TTIMEOUT,MIN specifications. This can be accomplished by the Master issuing a STOP condition at the
conclusion of the byte transfer in progress. When slave, the I2C must not cumulatively extend its clock
cycles for a period greater than TLOW:SEXT during any message from the initial START to the STOP.
When CSMBCLK TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF.
Figure 17-10. Timeout measurement intervals
Note: CSMBCLK TIMEOUT SEXT and MEXT are optional functions that are implemented in second
step.
Stop
Start
T
LOW:SEXT
T
LOW:MEXT
T
LOW:MEXT
T
LOW:MEXT
Clk
Ack
Clk
Ack
SCL
SDA
