Fast Ethernet Controller (FEC)
16-2
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
16.1.2
Block Diagram
shows the block diagram of the FEC. The FEC is implemented with a combination of
hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3
standards.
Figure 16-1. FEC Block Diagram
The descriptor controller is a RISC-based controller providing these functions in the FEC:
•
Initialization (those internal registers not initialized by you or hardware)
•
High level control of the DMA channels (initiating DMA transfers)
•
Interpreting buffer descriptors
•
Address recognition for receive frames
•
Random number generation for transmit collision backoff timer
The RAM is the focal point of all data flow in the Fast Ethernet controller and divides into transmit and
receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from
the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the
transmit block, and receive data flows from the receive block into the receive FIFO.
FIFO
FEC DMA
MII
Receive
Transmit
Controller
I/O
PAD
MDO
MDEN
MDI
MII/7-Wire data
FIFO
RAM
FEC Bus
option
FEC_TXEN
FEC_TXD[3:0]
FEC_TXER
FEC_TXCLK
FEC_CRS
FEC_COL
FEC_RXCLK
FEC_RXDV
FEC_RXD[3:0]
FEC_RXER
FEC_MDC
FEC_MDIO
RAM
Internal Bus
Control/Status
Descriptor
Controller
Bus
Controller
(RISC +
microcode)
Registers
Interface
Internal Bus
Crossbar Switch
Master Bus
Interface
