MCF51CN128 Reference Manual
, Rev. 6
Freescale Semiconductor
9-1
Chapter 9
Parallel Input/Output Control
9.1
Overview of MCF51CN128 I/O Functions
9.1.1
Summary
This section explains software controls related to parallel input/output (I/O) and pin control. The
MCF51CN128 series MCUs have up to nine parallel I/O ports which include a total of 70 I/O pins. See
Chapter 2, “Pins and Connections,”
for more information about pin assignments and external hardware
considerations of these pins.
summarizes capabilities for the MCF51CN128 on a per port basis.
9.1.2
Ports Implemented via Rapid GPIO
Ports D and F are implemented using Rapid GPIO functions which are integrated as part of the ColdFire
core to improve edge resolution on those pins. RGPIO provides functionality similar to standard GPIO
with the addition of set/clear/toggle functionality, but at CPU (rather than peripheral bus clock) rates.
Table 9-1. Functionality on a Per Port Basis
Port Name
Width
GPIO Implementation
1
1
D[6] GPIO is output only.
Keyboard Interface
Pin Control
2
2
PE = pull-up enable, SE = slew rate enable, DS = drive strength control, IFE = input filter enable
PTA
8
GPIO[7:0]
—
PE, SE, DS, IFE
PTB
8
GPIO[7:0]
—
PE, SE, DS, IFE
PTC
8
GPIO[7:0]
—
PE, SE, DS, IFE
PTD
3
3
When PTD6 is set as RGPIO output, and "1" is driven to PTD6 by the RGPIO function, a read of register
RGPIODATA6 always return a 0 because V1 RGPIO design looks for IO enable when the return value of RGPIO
function reads data. As PTD6 is set to RGPIO output only, it returns 0 always to RGPIODATA6, athough PTD6 pin is
driven high.
8
GPIO/RGPIO[7:0]
—
PE, SE, DS, IFE
PTE
8
GPIO[7:0]
KBI2
PE, SE, DS, IFE
PTF
8
GPIO/RGPIO[15:8]
—
PE, SE, DS, IFE
PTG
8
GPIO[7:0]
KBI1
PE, SE, DS, IFE
PTH
8
GPIO[7:0]
—
PE, SE, DS, IFE
PTJ
6
GPIO[7:0]
—
PE, SE, DS, IFE
