NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 5-13
7 6 5 4 3 2 1 0
R POR PIN COP ILOP ILAD LOC LVD 0
W Writing any value to SRS address clears COP watchdog timer.
POR: 1 0 0 0 0 0 1 0
LVD: U 0 0 0 0 0 1 0
Any other
reset:
0 _
1
_
1
_
1
_
1
0 0 0
1
Any of these reset sources that are active at the time of reset entry causes the corresponding bit to set; bits corresponding to
sources that are not active at the time of reset entry are cleared.
2
U = Unaffected by MCU Reset.
Figure 5-2. System Reset Status (SRS)
Table 5-5. SRS Register Field Descriptions
Field Description
7
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by clearing SOPT1[COPT].
0 Reset not caused by COP time-out.
1 Reset caused by COP time-out.
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. This includes
any illegal instruction [except the ILLEGAL (0x4AFC) opcode] or a privilege violation (execution of a privileged
instruction in user mode). The STOP instruction is considered illegal if stop is disabled by both SOPT[STOPE,
WAITE] being cleared. The HALT instruction is considered illegal if the BDM interface is disabled by clearing
XCSR[ENBDM].
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
3
ILAD
Illegal Address — Reset was caused by the processor's attempted access of an illegal address in the memory
map, an address error, an RTE format error or the fault-on-fault condition. All the illegal address resets are
enabled when CPUCR[ARD] is cleared. When CPUCR[ARD] is set, then the appropriate processor exception is
generated instead of the reset, or if a fault-on-fault condition is reached, the processor simply halts.
0 Reset not caused by an illegal access.
1 Reset caused by an illegal access.