Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
5-9
The CPU configuration register (CPUCR) within the supervisor programming model allows you to
determine if specific ColdFire exception conditions are to generate a normal exception or a system reset.
The default state of the CPUCR forces a system reset for any of the exception types listed in
Table 5-3. ColdFire Exception Vector Table
1
Vector
Number
Exception Reset
Disabled
via CPUCR
Reported using SRS
64-108
I/O Interrupts
N/A
—
61
Unsupported instruction
N/A
—
47
Trap #15
N/A
—
46
Trap #14
N/A
—
45
Trap #13
N/A
—
44
Trap #12
N/A
—
43
Trap #11
N/A
—
42
Trap #10
N/A
—
41
Trap #9
N/A
—
40
Trap #8
N/A
—
39
Trap #7
N/A
—
38
Trap #6
N/A
—
37
Trap #5
N/A
—
36
Trap #4
N/A
—
35
Trap #3
N/A
—
34
Trap #2
N/A
—
33
Trap #1
N/A
—
32
Trap #0
N/A
—
24
Spurious IRQ
N/A
—
14
Format error
CPUCR[31]
ilad
12
Debug breakpoint IRQ
N/A
—
11
Illegal LineF
CPUCR[30]
ilop
10
Illegal LineA
CPUCR[30]
ilop
9
Trace
N/A
—
8
Privileged Violation
CPUCR[30]
ilop
4
Illegal instruction
CPUCR[30]
ilop
2
3
Address error
CPUCR[31]
ilad
2
Access error
CPUCR[31]
ilad
n/a
Flt-on-Flt Halt
CPUCR[31]
ilad
