NXP Semiconductors freescale MC92604, User Manual, Page: 18 / 56

Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
2-6 Freescale Semiconductor
Figure 2-3 depicts SW1 settings for using an onboard oscillator with the divide-by-two function set for the
MC92604 and 3.3V_CLK_OUT n SMA outputs. The 3.3V_CLK_OUT1 and 3.3V_CLK_OUT2 SMA
outputs are enabled and set to the divide-by-one function. The 3.3V_CLK_OUT3 and 3.3V_CLK_OUT4
SMA outputs are also enabled and are set to the divide-by-two function.
Figure 2-3. Reference Clock Selection Example Switch Settings
2.5 Interface Components
The following sections list the descriptions of the MC92604DVB interface connector components.
2.5.1 Parallel Inputs and Outputs
The MC92604 parallel I/O is supplied by the V
DDQ
voltage regulator (set for 2.5 or 3.3 V) and has a
rail-to-rail signal swing. The MC92604DVB is shipped with V
DDQ
set at 3.3 V.
Table 2-2. SW1 Settings and Output Frequencies
SW1
Switch
Switch
Position
REF_CLK_P, REF_CLK_N,
DIFF_CLK_OUT5, DIFF_CLK_OUT6
3.3V_CLK_OUT1,
3.3V_CLK_OUT2
3.3V_CLK_OUT3,
3.3V_CLK_OUT4
3 On CLK_IN N/A N/A
Off CLK_IN/2 N/A N/A
5 On N/A CLK_IN N/A
Off N/A CLK_IN/2 N/A
6 On N/A N/A CLK_IN
Off N/A N/A CLK_IN/2
1
2
3
4
5
6
On
SW1
3.3V_CLK_OUT 3, _OUT4 Frequency Select
3.3V_CLK_OUT 1, _OUT2 Frequency Select
MC100ES6222 Reset
MC92604 REF_CLK, Frequency select
Onboard/External CLK_IN Select
Alternate Oscillator ENABLE
7 MPC9456 Output ENABLE_B Reset
Clk_In/2
Clk_In/2
Reset
Clk_In/2
External
Y1
Enabled
Clk_In
Clk_In
Enabled
Clk_In
Onboard
Y2