NXP Semiconductors freescale KV4 Series, Reference Manual

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Table 3-4. Interrupt vector assignments (continued)
Address Vector IRQ Source description Source module
0x0000_01B0 108 92 CMP3 CMP3
0x0000_01B4 109 93 —
0x0000_01B8 110 94 FLexCAN1 OR'ed Message buffer (0-15) CAN1
0x0000_01BC 111 95 FLexCAN1 Bus Off CAN1
0x0000_01C0 112 96 FLexCAN1 Error CAN1
0x0000_01C4 113 97 FLexCAN1 Transmit Warning CAN1
0x0000_01C8 114 98 FLexCAN1 Receive Warning CAN1
0x0000_01CC 115 99 FLexCAN1 Wake Up CAN1
1
1. Don’t put the instruction to clear interrupt in last line of ISR
3.3 Asynchronous Wake-up Interrupt Controller (AWIC)
Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at
arm.com .
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Nested vectored
interrupt controller
(NVIC)
Wake-up
requests
Module
Module
Clock logic
Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration
Table 3-5. Reference links to related information
Topic Related module Reference
System memory map System memory map
Clocking Clock distribution
Power management Power management
Nested Vectored
Interrupt Controller
(NVIC)
NVIC
Wake-up requests AWIC wake-up sources
Chapter 3 Core overview
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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