NXP Semiconductors freescale KV4 Series, Reference Manual

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36.5.6 DAC Control Register 2 (DAC_C2)
Address: 4003_F000h base + 23h offset = 4003_F023h
Bit 7 6 5 4 3 2 1 0
Read
DACBFRP DACBFUP
Write
Reset 0 0 0 0 1 1 1 1
DAC_C2 field descriptions
Field Description
7–4
DACBFRP
DAC Buffer Read Pointer
In normal mode it keeps the current value of the buffer read pointer. FIFO mode, it is the FIFO read
pointer. It is writable in FIFO mode. User can configure it to same address to reset FIFO as empty.
DACBFUP DAC Buffer Upper Limit
In normal mode it selects the upper limit of the DAC buffer. The buffer read pointer cannot exceed it. In
FIFO mode it is the FIFO write pointer. User cannot set Buffer Up limit in FIFO mode. In Normal mode its
reset value is MAX. When IP is configured to FIFO mode, this register becomes Write_Pointer, and its
value is initially set to equal READ_POINTER automatically, and the FIFO status is empty. It is writable
and user can configure it to the same address to reset FIFO as empty.
36.6 Functional description
The 12-bit DAC module can select one of the two reference inputs—DACREF_1 and
DACREF_2 as the DAC reference voltage, V
in
by C0 [DACRFS]. See the chip-specific
DAC information to determine the source options for DACREF_1 and DACREF_2.
When the DAC is enabled, it converts the data in DACDAT0[11:0] or the data from the
DAC data buffer to a stepped analog output voltage. The output voltage range is from V
in
to V
in
∕4096, and the step is V
in
∕4096.
36.6.1 DAC data buffer operation
When the DAC is enabled and the buffer is not enabled, the DAC module always
converts the data in DAT0 to the analog output voltage.
When both the DAC and the buffer are enabled, the DAC converts the data in the data
buffer to analog output voltage. The data buffer read pointer advances to the next word
whenever a hardware or software trigger event occurs.
Chapter 36 12-bit Digital-to-Analog Converter (DAC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
761