NXP Semiconductors freescale KV4 Series, Reference Manual

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34.4.25 ADC Control Register 3 (ADC_CTRL3)
Address: 4005_C000h base + A8h offset = 4005_C0A8h
Bit 15 14 13 12 11 10 9 8
Read 0
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read 0
DMASRC SCNT1[2:0] SCNT0[2:0]
Write
Reset 0 0 0 0 0 0 0 0
ADC_CTRL3 field descriptions
Field Description
15–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
DMASRC
DMA Trigger Source
During sequential and simultaneous parallel scan modes CTRL3[DMASRC] selects between EOSI0 and
RDY bits as the DMA source. During non-simultaneous parallel scan mode CTRL3[DMASRC] selects
between EOSI0/EOSI1 for converters A and B, and the RDY bits as the DMA source.
0 DMA trigger source is end of scan interrupt
1 DMA trigger source is RDY bits
5–3
SCNT1[2:0]
Sample Window Count 1
During parallel non-simultaneous scan mode (CTRL2[SIMULT]=0) the CTRL3[SCNT1] bits are used to
control the sampling time of the first sample after a scan is initiated on converter B. During sequential and
parallel simultaneous scan modes, CTRL3[SCNT1] is ignored and the sampling window for converters A
and B is controlled by CTRL3[SCNT0]. The default value is 0 which corresponds to a sampling time of 2
ADC clocks. Each increment of CTRL3[SCNT1] corresponds to an additional ADC clock cycle of sampling
time with a maximum sampling time of 9 ADC clocks.
SCNT0[2:0] Sample Window Count 0
During sequential and parallel simultaneous scan modes (CTRL2[SIMULT]=1) the CTRL3[SCNT0] bits
control the sampling time of the first sample after a scan is initiated on both converters A and B. In parallel
non-simultaneous mode (CTRL2[SIMULT]=0) CTRL3[SCNT0] affects converter A only. The default value
is 0 which corresponds to a sampling time of 2 ADC clocks. Each increment of CTRL3[SCNT0]
corresponds to an additional ADC clock cycle of sampling time with a maximum sampling time of 9 ADC
clocks. In sequential scan mode the CTRL[SCNT0] setting will be ignored whenever the channel selected
for the next sample is on the other converter. In other words, during a sequential scan, if a sample
converts a converter A channel (ANA0-ANA7) and the next sample converts a converter B channel
(ANB0-ANB7) or vice versa, CTRL3[SCNT0] will be ignored and use the default sampling time for the next
sample.
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
703