NXP Semiconductors freescale KV4 Series, Reference Manual

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ADC_GC2 field descriptions (continued)
Field Description
00 x1 amplification
01 x2 amplification
10 x4 amplification
11 reserved
GAIN8 Gain Control Bit 8
GAIN 8 controls ANB0
00 x1 amplification
01 x2 amplification
10 x4 amplification
11 reserved
34.4.23 ADC Scan Control Register (ADC_SCTRL)
This register is an extension to the CLIST1-4 registers, providing the ability to pause and
await a new sync while processing samples programmed in the CLIST*[SAMPLE0–
SAMPLE15] fields.
These 16 control bits are used to determine whether a sample in a scan occurs
immediately or if the sample waits for an enabled sync input to occur. The sync input
must occur after the conversion of the current sample completes. During sequential mode
scans, the SCTRL[SC] bits are used in order from SC0 to SC15. During simultaneous
parallel scan modes, the bits are used in order from SC0 to SC3 and SC8 to SC11. In non-
simultaneous parallel scans, ADCA uses the bits in order from SC0 to SC3 followed by
SC8 to SC11. ADCB will use bits SC4 to SC7 followed by SC12 to SC15 in non-
simultaneous parallel scans.
When setting SCTRL[SC0], don’t set CTRL1[START0] or CTRL2[START1]. Just clear
CTRL1[STOP0] or CTRL2[STOP1] and the first enabled sync input will start the scan.
Setting SC0 delays sample 0 until a sync pulse occurs. Setting SC1 delays sample 1 until
a sync pulse occurs after completing sample 0.
Address: 4005_C000h base + A4h offset = 4005_C0A4h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
SC[15:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_SCTRL field descriptions
Field Description
SC[15:0] Scan Control Bits
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
701