Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
1
0
1
0
0
1
1
1
ADC_PWR field descriptions
Field
Description
15
ASB
Auto Standby
This bit selects auto-standby mode. PWR[ASB] is ignored if PWR[APD] is 1. When the ADC is idle, auto-
standby mode selects the standby clock as the ADC clock source and puts the converters into standby
current mode. At the start of any scan, the conversion clock is selected as the ADC clock and then a delay
of PWR[PUDELAY] ADC clock cycles is imposed for current levels to stabilize. After this delay, the ADC
will initiate the scan. When the ADC returns to the idle state, the standby clock is again selected and the
converters revert to the standby current state.
This mode is not recommended for conversion clock rates at or below 100kHz. Instead, set PWR[ASB and
APD]=0 and use standby power mode (normal mode with a sufficiently slow conversion clock so that
standby current mode automatically engages). This provides the advantages of standby current mode
while avoiding the clock switching and the PWR[PUDELAY].
Set PWR[ASB] prior to clearning PWR[PD1/0].
0
Auto standby mode disabled
1
Auto standby mode enabled
14–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
11
PSTS1
ADC Converter B Power Status
This bit is asserted immediately following a write of "1" to PWR[PD1]. It is de-asserted PWR[PUDELAY]
ADC clock cycles after a write of "0" to PWR[PD1] if PWR[APD] is "0". This bit can be read as a status bit
to determine when the ADC is ready for operation. During auto-powerdown mode, this bit indicates the
current powered state of converter B.
0
ADC Converter B is currently powered up
1
ADC Converter B is currently powered down
10
PSTS0
ADC Converter A Power Status
This bit is asserted immediately following a write of "1" to PWR[PD0]. It is de-asserted PWR[PUDELAY]
ADC clock cycles after a write of "0" to PWR[PD0] if PWR[APD] is "0". This bit can be read as a status bit
to determine when the ADC is ready for operation. During auto-powerdown mode, this bit indicates the
current powered state of converter A.
0
ADC Converter A is currently powered up
1
ADC Converter A is currently powered down
9–4
PUDELAY
Power Up Delay
This 6-bit field determines the number of ADC clocks provided to power up an ADC converter (after setting
PWR[PD0 or PD1] to 0) before allowing a scan to start. It also determines the number of ADC clocks of
delay provided in auto-powerdown (APD) and auto-standby (ASB) modes between when the ADC goes
from the idle to active state and when the scan is allowed to start. The default value is 26 ADC clocks.
Accuracy of the initial conversions in a scan will be degraded if PWR[PUDELAY] is set to too small a
value.
Table continues on the next page...
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
695
Summary of Contents for freescale KV4 Series
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