34.4.10 ADC Status Register (ADC_STAT)
This register provides the current status of the ADC module. STAT[HLMTI and LLMTI]
bits are cleared by writing 1s to all asserted bits in the limit status register, LIMSTAT.
Likewise, the STAT[ZCI] bit, is cleared by writing 1s to all asserted bits in the zero
crossing status register, ZXSTAT. The STAT[EOSIx] bits are cleared by writing a one to
them.
Except for STAT[CIP0 and CIP1] this register's bits are sticky. Once set to a one state,
they require some specific action to clear them. They are not cleared automatically on the
next scan sequence.
Address: 4005_C000h base + 12h offset = 4005_C012h
Bit
15
14
13
12
11
10
9
8
Read
Write
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
ADC_STAT field descriptions
Field
Description
15
CIP0
Conversion in Progress
This bit indicates whether a scan is in progress. This refers to any scan except a B converter scan in non-
simultaneous parallel scan modes.
0
Idle state
1
A scan cycle is in progress. The ADC will ignore all sync pulses or start commands
14
CIP1
Conversion in Progress
This bit indicates whether a scan is in progress. This refers only to a B converter scan in non-simultaneous
parallel scan modes.
0
Idle state
1
A scan cycle is in progress. The ADC will ignore all sync pulses or start commands
13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
EOSI1
End of Scan Interrupt
This bit indicates whether a scan of analog inputs have been completed since the last read of the status
register or since a reset. This bit is cleared by writing a one to it. This bit cannot be set by software.
In looping scan modes, this interrupt is triggered at the completion of each iteration of the loop.
Table continues on the next page...
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
687
Summary of Contents for freescale KV4 Series
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