NXP Semiconductors freescale KV4 Series, Reference Manual

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XBARA_CTRL0 field descriptions (continued)
Field Description
Restriction: IEN0 and DEN0 should not both be set to 1.
0 DMA disabled
1 DMA enabled
26.4.32 Crossbar A Control Register 1 (XBARA_CTRL1)
Use this register to configure edge detection, interrupt, and DMA features for the
XBAR_OUT2 and XBAR_OUT3 outputs.
The XBAR_CTRL registers are organized similarly to the XBAR_SEL registers, with
control fields for two XBAR_OUT outputs in each register. In control register 1, the
LSBs contain the control fields for XBAR_OUT2, and the MSBs contain the control
fields for XBAR_OUT3.
Address: 4005_9000h base + 3Eh offset = 4005_903Eh
Bit 15 14 13 12 11 10 9 8
Read 0 STS3
EDGE3 IEN3 DEN3
Write w1c
Reset
0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read 0 STS2
EDGE2 IEN2 DEN2
Write w1c
Reset 0 0 0 0 0 0 0 0
XBARA_CTRL1 field descriptions
Field Description
15–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
STS3
Edge detection status for XBAR_OUT3
This bit reflects the results of edge detection for XBAR_OUT3.
This field is set to 1 when an edge consistent with the current setting of EDGE3 is detected on
XBAR_OUT3. This field is cleared by writing 1 to it or by a DMA_ACK3 reception when DEN3 is set.
Writing 0 to the field has no effect.
When interrupt or DMA functionality is enabled for XBAR_OUT3, this field is 1 when the interrupt or DMA
request is asserted and 0 when the interrupt or DMA request has been cleared.
0 Active edge not yet detected on XBAR_OUT3
1 Active edge detected on XBAR_OUT3
Table continues on the next page...
Memory Map and Register Descriptions
KV4x Reference Manual, Rev. 2, 02/2015
508
Preliminary
Freescale Semiconductor, Inc.