NXP Semiconductors freescale KV4 Series, Reference Manual

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DMA_DCHPRIn field descriptions (continued)
Field Description
6
DPA
Disable Preempt Ability.
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
5–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CHPRI Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled
NOTE: Reset value for the channel priority field, CHPRI, is equal to the corresponding channel number
for each priority register, that is, DCHPRI15[CHPRI] = 0b1111.
23.3.18 TCD Source Address (DMA_TCDn_SADDR)
Address: 4000_8000h base + 1000h (32d × i), where i=0d to 15d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SADDR
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
DMA_TCDn_SADDR field descriptions
Field Description
SADDR Source Address
Memory address pointing to the source data.
23.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)
Address: 4000_8000h base + 1004h (32d × i), where i=0d to 15d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
SOFF
Write
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
Chapter 23 Direct Memory Access Controller (eDMA)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
411