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UARTx_RWFIFO field descriptions
Field
Description
RXWATER
Receive Watermark
When the number of datawords in the receive FIFO/buffer is equal to or greater than the value in this
register field, an interrupt via S1[RDRF] or a DMA request via C5[RDMAS] is generated as determined by
C5[RDMAS] and C2[RIE]. For proper operation, the value in RXWATER must be set to be less than the
receive FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be greater
than 0.
46.4.21 UART FIFO Receive Count (UARTx_RCFIFO)
This is a read only register that indicates how many datawords are currently in the receive
FIFO/buffer. It may be read at any time.
Address: Base a 16h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
UARTx_RCFIFO field descriptions
Field
Description
RXCOUNT
Receive Counter
The value in this register indicates the number of datawords that are in the receive FIFO/buffer. If a
dataword is being received, that is, in the receive shift register, it is not included in the count. This value
may be used in conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the receive
FIFO/buffer.
46.5 Functional description
This section provides a complete functional description of the UART block.
The UART allows full duplex, asynchronous, NRZ serial communication between the
CPU and remote devices, including other CPUs. The UART transmitter and receiver
operate independently, although they use the same baud rate generator. The CPU
monitors the status of the UART, writes the data to be transmitted, and processes
received data.
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
1294
Preliminary
Freescale Semiconductor, Inc.
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