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NXP Semiconductors freescale KV4 Series, Reference Manual

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NXP Semiconductors freescale KV4 Series Reference Manual Download Page 1236

I2C_F field descriptions (continued)

Field

Description

MULT

ICR

Hold times (μs)

SDA

SCL Start

SCL Stop

0h

18h

1.125

4.750

5.125

45.4.3 I2C Control Register 1 (I2C_C1)

Address: 4006_6000h base + 2h offset = 4006_6002h

Bit

7

6

5

4

3

2

1

0

Read

IICEN

IICIE

MST

TX

TXAK

0

WUEN

DMAEN

Write

RSTA

Reset

0

0

0

0

0

0

0

0

I2C_C1 field descriptions

Field

Description

7

IICEN

I2C Enable

Enables I2C module operation.

0

Disabled

1

Enabled

6

IICIE

I2C Interrupt Enable

Enables I2C interrupt requests.

0

Disabled

1

Enabled

5

MST

Master Mode Select

When MST is changed from 0 to 1, a START signal is generated on the bus and master mode is selected.
When this bit changes from 1 to 0, a STOP signal is generated and the mode of operation changes from
master to slave.

0

Slave mode

1

Master mode

4

TX

Transmit Mode Select

Selects the direction of master and slave transfers. In master mode this bit must be set according to the
type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave
this bit must be set by software according to the SRW bit in the status register.

0

Receive

1

Transmit

Table continues on the next page...

Memory map/register definition

KV4x Reference Manual, Rev. 2, 02/2015

1236

Preliminary

Freescale Semiconductor, Inc.

Summary of Contents for freescale KV4 Series

Page 1: ...KV4x Reference Manual Supports MKV46 MKV45 MKV44 MKV43 MKV41 MKV40 part numbers Document Number KV4XP100M150RM Rev 2 02 2015 Preliminary...

Page 2: ...KV4x Reference Manual Rev 2 02 2015 2 Preliminary Freescale Semiconductor Inc...

Page 3: ...4 Core Modules 64 2 2 2 System Modules 65 2 2 3 Memories and Memory Interfaces 66 2 2 4 Clocks 66 2 2 5 Security and Integrity modules 66 2 2 6 Analog modules 67 2 2 7 Timer modules 67 2 2 8 Communica...

Page 4: ...Chapter 4 Memories and Memory Interfaces 4 1 Flash memory types 83 4 2 Flash Memory Sizes 83 4 3 Flash Security 84 4 4 Flash Modes 84 4 5 Erase All Flash Contents 84 4 6 FTFA_FOPT Register 85 4 7 SRAM...

Page 5: ...5 2 WDOG clocking 101 6 5 3 Debug trace clock 102 6 5 4 PMC 1 kHz LPO clock 102 6 5 5 PORT digital filter clocking 102 6 5 6 LPTMR clocking 103 6 5 7 FlexCAN clocking 103 6 5 8 UART clocking 104 6 6...

Page 6: ...erences 119 9 2 The Debug Port 119 9 2 1 JTAG to SWD change sequence 119 9 3 Debug Port Pin Descriptions 120 9 4 JTAG status and control registers 120 9 4 1 MDM AP Control Register 121 9 4 2 MDM AP St...

Page 7: ...reset LOCKUP 133 10 2 2 8 MDM AP system reset request 133 10 2 3 Debug resets 133 10 2 3 1 JTAG reset 133 10 2 3 2 nTRST reset 134 10 2 3 3 Resetting the Debug subsystem 134 10 3 Boot 135 10 3 1 Boot...

Page 8: ...2 Global Pin Control Low Register PORTx_GPCLR 163 12 5 3 Global Pin Control High Register PORTx_GPCHR 163 12 5 4 Interrupt Status Flag Register PORTx_ISFR 164 12 5 5 Digital Filter Enable Register PO...

Page 9: ...ting Control Register 7 SIM_SCGC7 194 13 2 13 System Clock Divider Register 1 SIM_CLKDIV1 194 13 2 14 Flash Configuration Register 1 SIM_FCFG1 197 13 2 15 Flash Configuration Register 2 SIM_FCFG2 198...

Page 10: ...ypes 222 14 2 5 1 Ping packet 222 14 2 5 2 Ping Response Packet 223 14 2 5 3 Framing Packet 223 14 2 5 4 Command packet 225 14 2 5 5 Data packet 227 14 2 5 6 Response packet 227 14 2 6 Flashloader Com...

Page 11: ...er descriptions 255 15 2 1 System Reset Status Register 0 RCM_SRS0 256 15 2 2 System Reset Status Register 1 RCM_SRS1 257 15 2 3 Reset Pin Filter Control register RCM_RPFC 259 15 2 4 Reset Pin Filter...

Page 12: ...278 16 4 3 3 High Speed Run HSRUN mode 278 16 4 4 Wait modes 279 16 4 4 1 WAIT mode 279 16 4 4 2 Very Low Power Wait VLPW mode 280 16 4 5 Stop modes 280 16 4 5 1 STOP mode 281 16 4 5 2 Very Low Power...

Page 13: ...system 295 18 3 1 LVD reset operation 296 18 3 2 LVD interrupt operation 296 18 3 3 Low voltage warning LVW interrupt operation 296 18 4 I O retention 297 18 5 Memory map and register descriptions 29...

Page 14: ...register LLWU_PE8 315 19 4 9 LLWU Module Enable register LLWU_ME 316 19 4 10 LLWU Pin Flag 1 register LLWU_PF1 317 19 4 11 LLWU Pin Flag 2 register LLWU_PF2 319 19 4 12 LLWU Pin Flag 3 register LLWU_P...

Page 15: ...bridges 337 21 2 Memory map 337 21 3 PACR registers 337 21 4 AIPS_Lite PACRE P register reset values 337 21 5 Introduction 338 21 5 1 Features 338 21 5 2 General operation 338 21 6 Memory map register...

Page 16: ...22 5 3 Always enabled DMA sources 361 22 6 Initialization application information 363 22 6 1 Reset 363 22 6 2 Enabling and configuring sources 363 Chapter 23 Direct Memory Access Controller eDMA 23 1...

Page 17: ...nnel n Priority Register DMA_DCHPRIn 410 23 3 18 TCD Source Address DMA_TCDn_SADDR 411 23 3 19 TCD Signed Source Address Offset DMA_TCDn_SOFF 411 23 3 20 TCD Transfer Attributes DMA_TCDn_ATTR 412 23 3...

Page 18: ...ates 431 23 4 4 2 Peak request rates 432 23 4 4 3 eDMA performance example 434 23 5 Initialization application information 435 23 5 1 eDMA initialization 435 23 5 2 Programming errors 437 23 5 3 Arbit...

Page 19: ...2 Modes of Operation 453 24 2 2 1 Stop Mode 453 24 2 2 2 Debug Mode 453 24 2 3 Block Diagram 453 24 3 EWM Signal Descriptions 454 24 4 Memory Map Register Definition 454 24 4 1 Control Register EWM_C...

Page 20: ...esting the watchdog 468 25 5 1 Quick test 469 25 5 2 Byte test 469 25 6 Backup reset generator 471 25 7 Generated resets and interrupts 471 25 8 Memory map and register definition 472 25 8 1 Watchdog...

Page 21: ...ssignment 483 26 1 2 XBARA signal output assignment 484 26 2 Introduction 486 26 2 1 Overview 486 26 2 2 Features 487 26 2 3 Modes of Operation 487 26 2 4 Block Diagram 487 26 3 Signal Descriptions 48...

Page 22: ..._SEL16 499 26 4 18 Crossbar A Select Register 17 XBARA_SEL17 499 26 4 19 Crossbar A Select Register 18 XBARA_SEL18 500 26 4 20 Crossbar A Select Register 19 XBARA_SEL19 500 26 4 21 Crossbar A Select R...

Page 23: ...RB_SEL0 515 27 3 2 Crossbar B Select Register 1 XBARB_SEL1 516 27 3 3 Crossbar B Select Register 2 XBARB_SEL2 516 27 3 4 Crossbar B Select Register 3 XBARB_SEL3 517 27 3 5 Crossbar B Select Register 4...

Page 24: ...3 29 3 Block Diagram 534 29 4 OSC Signal Descriptions 534 29 5 External Crystal Resonator Connections 535 29 6 External Clock Connections 536 29 7 Memory Map Register Definitions 537 29 7 1 OSC Memory...

Page 25: ..._C2 551 30 3 3 MCG Control 3 Register MCG_C3 552 30 3 4 MCG Control 4 Register MCG_C4 553 30 3 5 MCG Control 5 Register MCG_C5 554 30 3 6 MCG Control 6 Register MCG_C6 555 30 3 7 MCG Status Register M...

Page 26: ...External Crystal 16 MHz MCGOUTCLK frequency 120 MHz 573 30 5 3 2 Example 2 Moving from PEE to BLPI mode MCGOUTCLK frequency 32 kHz 577 Chapter 31 Flash Memory Controller FMC 31 1 Introduction 581 31 1...

Page 27: ...4 18 Cache Data Storage mid lower word FMC_DATAW2SnML 600 31 4 19 Cache Data Storage lowermost word FMC_DATAW2SnLM 600 31 4 20 Cache Data Storage uppermost word FMC_DATAW3SnUM 601 31 4 21 Cache Data...

Page 28: ...TFA_FPROTn 620 32 3 3 7 Execute only Access Registers FTFA_XACCn 622 32 3 3 8 Supervisor only Access Registers FTFA_SACCn 623 32 3 3 9 Flash Access Segment Size Register FTFA_FACSS 624 32 3 3 10 Flash...

Page 29: ...Backdoor Access Key Command 647 32 4 11 Security 648 32 4 11 1 Changing the Security State 649 32 4 12 Reset Sequence 650 Chapter 33 Cyclic redundancy check CRC 33 1 Introduction 651 33 1 1 Features...

Page 30: ...C channel muxing 662 34 2 Introduction 662 34 2 1 Overview 662 34 2 2 Features 662 34 2 3 Block Diagram 664 34 3 Signal Descriptions 664 34 3 1 Overview 664 34 3 2 External Signal Descriptions 665 34...

Page 31: ...High Limit Registers ADC_HILIMn 693 34 4 18 ADC Offset Registers ADC_OFFSTn 693 34 4 19 ADC Power Control Register ADC_PWR 694 34 4 20 ADC Calibration Register ADC_CAL 697 34 4 21 Gain Control 1 Regis...

Page 32: ...al window sample input 725 35 2 Introduction 725 35 2 1 CMP features 725 35 2 2 6 bit DAC key features 726 35 2 3 ANMUX key features 727 35 2 4 CMP DAC and ANMUX diagram 727 35 2 5 CMP block diagram 7...

Page 33: ...t mode operation 746 35 4 2 2 Stop mode operation 747 35 4 2 3 Background Debug Mode Operation 747 35 4 3 Startup and operation 747 35 4 4 Low pass filter 747 35 4 4 1 Enabling filter modes 748 35 4 4...

Page 34: ...36 5 3 DAC Status Register DAC_SR 758 36 5 4 DAC Control Register DAC_C0 759 36 5 5 DAC Control Register 1 DAC_C1 760 36 5 6 DAC Control Register 2 DAC_C2 761 36 6 Functional description 761 36 6 1 DA...

Page 35: ...k Signal 772 37 4 Memory Map and Registers 772 37 4 1 Counter Register PWMA_SMnCNT 780 37 4 2 Initial Count Register PWMA_SMnINIT 780 37 4 3 Control 2 Register PWMA_SMnCTRL2 781 37 4 4 Control Registe...

Page 36: ...ister PWMA_SMnCAPTCOMPB 806 37 4 29 Capture Control X Register PWMA_SMnCAPTCTRLX 807 37 4 30 Capture Compare X Register PWMA_SMnCAPTCOMPX 809 37 4 31 Capture Value 0 Register PWMA_SMnCVAL0 809 37 4 32...

Page 37: ...5 37 5 Functional Description 826 37 5 1 PWM Capabilities 826 37 5 1 1 Center Aligned PWMs 826 37 5 1 2 Edge Aligned PWMs 828 37 5 1 3 Phase Shifted PWMs 829 37 5 1 4 Double Switching PWMs 830 37 5 1...

Page 38: ...pter 38 Programmable Delay Block PDB 38 1 Chip specific PDB information 863 38 1 1 PDB Instantiation 863 38 1 1 1 PDB0 Output Triggers 863 38 1 1 2 PDB0 Input Trigger Connections 863 38 1 1 3 PDB1 Out...

Page 39: ...ay 0 register PDBx_CHnDLY0 878 38 4 8 Channel n Delay 1 register PDBx_CHnDLY1 878 38 4 9 Channel n Delay 2 register PDBx_CHnDLY2 879 38 4 10 Channel n Delay 3 register PDBx_CHnDLY3 879 38 4 11 DAC Int...

Page 40: ...dule instances 891 39 1 8 FTM output triggers for other modules 891 39 1 9 FTM Global Time Base 892 39 1 10 FTM BDM and debug halt mode 893 39 2 Introduction 893 39 2 1 FlexTimer philosophy 893 39 2 2...

Page 41: ...Capture Filter Control FTMx_FILTER 932 39 4 20 Fault Control FTMx_FLTCTRL 933 39 4 21 Quadrature Decoder Control And Status FTMx_QDCTRL 936 39 4 22 Configuration FTMx_CONF 938 39 4 23 FTM Fault Input...

Page 42: ...CnV register update 972 39 5 11 PWM synchronization 973 39 5 11 1 Hardware trigger 973 39 5 11 2 Software trigger 974 39 5 11 3 Boundary cycle and loading points 975 39 5 11 4 MOD register synchroniz...

Page 43: ...9 5 24 1 One Shot Capture mode 1007 39 5 24 2 Continuous Capture mode 1008 39 5 24 3 Pulse width measurement 1008 39 5 24 4 Period measurement 1010 39 5 24 5 Read coherency mechanism 1012 39 5 25 Quad...

Page 44: ..._LDVALn 1031 40 4 3 Current Timer Value Register PIT_CVALn 1031 40 4 4 Timer Control Register PIT_TCTRLn 1032 40 4 5 Timer Flag Register PIT_TFLGn 1033 40 5 Functional description 1033 40 5 1 General...

Page 45: ...SEB 1044 41 3 3 Index Input INDEX 1044 41 3 4 Home Switch Input HOME 1045 41 3 5 Trigger Input TRIGGER 1045 41 3 6 Position Match Output POSMATCH 1045 41 4 Memory Map and Registers 1046 41 4 1 Control...

Page 46: ...0 Lower Position Compare Register ENC_LCOMP 1060 41 5 Functional Description 1060 41 5 1 Positive versus Negative Direction 1061 41 5 2 Prescaler for Slow or Fast Speed Measurement 1061 41 5 3 Holding...

Page 47: ...ed 1071 42 5 3 2 Prescaler bypassed 1071 42 5 3 3 Glitch filter 1071 42 5 3 4 Glitch filter bypassed 1071 42 5 4 LPTMR compare 1072 42 5 5 LPTMR counter 1072 42 5 6 LPTMR hardware trigger 1073 42 5 7...

Page 48: ...1 register CANx_IFLAG1 1108 43 4 12 Control 2 register CANx_CTRL2 1111 43 4 13 Error and Status 2 register CANx_ESR2 1115 43 4 14 CRC Register CANx_CRCR 1116 43 4 15 Rx FIFO Global Mask register CANx...

Page 49: ...1 Remote frames 1149 43 5 8 2 Overload frames 1150 43 5 8 3 Time stamp 1151 43 5 8 4 Protocol timing 1151 43 5 8 5 Arbitration and matching timing 1155 43 5 8 6 Tx Arbitration start delay 1156 43 5 9...

Page 50: ...PI Doze Mode 1171 44 1 10 SPI Interrupts 1171 44 2 Introduction 1171 44 2 1 Block Diagram 1171 44 2 2 Features 1172 44 2 3 Interface configurations 1174 44 2 3 1 SPI configuration 1174 44 2 4 Modes of...

Page 51: ...4 4 8 PUSH TX FIFO Register In Slave Mode SPI_PUSHR_SLAVE 1197 44 4 9 POP RX FIFO Register SPI_POPR 1198 44 4 10 Transmit FIFO Registers SPI_TXFRn 1198 44 4 11 Receive FIFO Registers SPI_RXFRn 1199 44...

Page 52: ...omplete Interrupt Request 1223 44 5 7 4 Transmit FIFO Underflow Interrupt Request 1223 44 5 7 5 Receive FIFO Drain Interrupt or DMA Request 1223 44 5 7 6 Receive FIFO Overflow Interrupt Request 1223 4...

Page 53: ...I2C_C1 1236 45 4 4 I2C Status register I2C_S 1237 45 4 5 I2C Data I O register I2C_D 1239 45 4 6 I2C Control Register 2 I2C_C2 1240 45 4 7 I2C Programmable Input Glitch Filter Register I2C_FLT 1241 4...

Page 54: ...FAST ACK and NACK 1256 45 5 5 Resets 1256 45 5 6 Interrupts 1256 45 5 6 1 Byte transfer interrupt 1257 45 5 6 2 Address detect interrupt 1257 45 5 6 3 Stop Detect Interrupt 1258 45 5 6 4 Exit from low...

Page 55: ...trol Register 2 UARTx_C2 1275 46 4 5 UART Status Register 1 UARTx_S1 1277 46 4 6 UART Status Register 2 UARTx_S2 1280 46 4 7 UART Control Register 3 UARTx_C3 1281 46 4 8 UART Data Register UARTx_D 128...

Page 56: ...8 46 5 1 6 Hardware flow control 1298 46 5 1 7 Transceiver driver enable 1299 46 5 2 Receiver 1300 46 5 2 1 Receiver character length 1301 46 5 2 2 Receiver bit ordering 1301 46 5 2 3 Character recept...

Page 57: ...cations 1323 46 9 3 1 Overrun operation 1323 46 9 4 Match address registers 1324 46 9 5 Modem feature 1324 46 9 5 1 Ready to receive using RTS 1325 46 9 5 2 Transceiver driver enable using RTS 1325 46...

Page 58: ...output 1334 Chapter 48 JTAG Controller JTAGC 48 1 Introduction 1337 48 1 1 Block diagram 1337 48 1 2 Features 1338 48 1 3 Modes of operation 1338 48 1 3 1 Reset 1338 48 1 3 2 IEEE 1149 1 2001 defined...

Page 59: ...1 2001 register 1345 48 4 4 JTAGC block instructions 1345 48 4 4 1 IDCODE instruction 1346 48 4 4 2 SAMPLE PRELOAD instruction 1346 48 4 4 3 SAMPLE instruction 1346 48 4 4 4 EXTEST External test instr...

Page 60: ...KV4x Reference Manual Rev 2 02 2015 60 Preliminary Freescale Semiconductor Inc...

Page 61: ...dentify different numbering systems This suffix Identifies a b Binary number For example the binary equivalent of the number 5 is written 101b In some cases binary numbers are shown with the prefix 0b...

Page 62: ...4 XAD 7 0 Numbers in brackets and separated by a colon represent either A subset of a register s named field For example REVNO 6 4 refers to bits 6 4 that are part of the COREREV field that occupies...

Page 63: ...nit based on ARMv7 M architecture up to 150 MHz operating frequency System System integration module SIM Power management and mode controllers PMC Multiple power modes available based on run wait stop...

Page 64: ...ments include an ARMv7 Thumb 2 DSP ported from the ARMv7 A R profile architectures providing 32 bit instructions with SIMD single instruction multiple data DSP style multiply accumulates and saturatin...

Page 65: ...sters and bus slaves allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave Peripheral bridges The perip...

Page 66: ...ing clock modules are available on this device Table 2 5 Clock modules Module Description Multi clock generator MCG The MCG provides several clock sources for the MCU that include Phase locked loop PL...

Page 67: ...on an external pin or set as one of the inputs to the comparator or ADC 2 2 7 Timer modules The following timer modules are available on this device Table 2 8 Timer modules Module Description Programm...

Page 68: ...mpare Interrupt generated on Timer Compare Hardware trigger generated on Timer Compare Pulse Width Modulator A PWMA eFlexPWM module contains four identical submodules with up to three outputs per subm...

Page 69: ...communication interfaces are available on this device Table 2 9 Communication modules Module Description Flex Controller Area Network FlexCAN Supports CAN protocol according to the CAN 2 0 B protocol...

Page 70: ...28 150 128 24 18 11 0 8 Yes 2 1 4 2 1 1 1 64 44F1283 150 128 24 13 6 0 8 Yes 2 1 4 2 1 1 1 48 44F64 150 64 16 18 11 0 8 Yes 2 1 4 2 1 1 1 64 44F643 150 64 16 13 6 0 8 Yes 2 1 4 2 1 1 1 48 43F128 150 1...

Page 71: ...8 channels and FTM1 2channels are available 8 2 FTM0 8 channels are available FTM1 2channels are available 3 Package Your Way Chapter 2 Introduction KV4x Reference Manual Rev 2 02 2015 Freescale Semic...

Page 72: ...Orderable part numbers and features KV4x Reference Manual Rev 2 02 2015 72 Preliminary Freescale Semiconductor Inc...

Page 73: ...figuration Table 3 1 Reference links to related information Topic Related module Reference Full description ARM Cortex M4 core ARM Cortex M4 Technical Reference Manual System memory map System memory...

Page 74: ...oupled to the upper half system RAM SRAM_U Private peripheral PPB bus The PPB provides access to these modules ARM modules such as the NVIC ITM DWT FBP and ROM table Freescale Miscellaneous Control Mo...

Page 75: ...Module PPB Figure 3 2 NVIC configuration 3 2 1 Interrupt priority levels This device supports 16 priority levels for interrupts Therefore in the NVIC each source in the IPR registers contains 4 bits...

Page 76: ...0000_0044 17 1 DMA channel 1 17 transfer complete DMA 0x0000_0048 18 2 DMA channel 2 18 transfer complete DMA 0x0000_004C 19 3 DMA channel 3 19 transfer complete DMA 0x0000_0050 20 4 DMA channel 4 20...

Page 77: ...46 30 0x0000_00BC 47 31 UART0 status sources UART0 0x0000_00C0 48 32 UART0 error sources UART0 0x0000_00C4 49 33 UART1 status sources UART1 0x0000_00C8 50 34 UART1 error sources UART1 0x0000_00CC 51 3...

Page 78: ...68 90 74 0x0000_016C 91 75 FLexCAN0 OR ed Message buffer 0 15 CAN0 0x0000_0170 92 76 FLexCAN0 Bus Off CAN0 0x0000_0174 93 77 FLexCAN0 Error CAN0 0x0000_0178 94 78 FLexCAN0 Transmit Warning CAN0 0x0000...

Page 79: ...er AWIC Configuration This section summarizes how the module has been configured in the chip Full documentation for this module is provided by ARM and can be found at arm com Asynchronous Wake up Inte...

Page 80: ...C Address match wakeup UART Active edge on RXD LPTMR Functional in Stop VLPS modes FlexCAN Functional in Stop mode NMI Non maskable interrupt 3 4 FPU Configuration This section summarizes how the modu...

Page 81: ...AG controller cJTAG Figure 3 5 JTAGC Controller configuration Table 3 8 Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port cont...

Page 82: ...JTAG Controller Configuration KV4x Reference Manual Rev 2 02 2015 82 Preliminary Freescale Semiconductor Inc...

Page 83: ...n a Package Your Way program for Kinetis MCUs Visit freescale com KPYW for more details Table 4 1 KV4x flash memory size Device Flash KB Block 0 flash address range MKV46F256VLL15 256 0000_0000 0003 _...

Page 84: ...flash memory is always configured in NVM normal There are no operating conditions in which the flash is configured for NVM special mode 4 5 Erase All Flash Contents An Erase All Flash Blocks operation...

Page 85: ...escale com KPYW for more details Table 4 2 SRAM size Freescale part number SRAM KB MKV46F256VLL15 32 MKV46F256VLH15 32 MKV46F128VLL15 24 MKV46F128VLH15 24 MKV44F128VLL15 24 MKV44F128VLH15 24 MKV44F128...

Page 86: ...AM_L and SRAM_U ranges form a contiguous block in the memory map As such SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address SRAM_U is anchored to 0x2000_0000 and occup...

Page 87: ...ined down to VLLS3 mode In VLLS2 the region of SRAM_U from 0x2000_0000 is powered In VLLS1 and VLLS0 no SRAM is retained 4 10 System Register file This device includes a 32 byte register file that is...

Page 88: ...System Register file KV4x Reference Manual Rev 2 02 2015 88 Preliminary Freescale Semiconductor Inc...

Page 89: ...paces that are intended for specific purposes There are two aliased address spaces that are mapped into the ICode regions address 0x2000_0000 for code sections that are normally located in the system...

Page 90: ...tband region for peripheral bridge 0 AIPS Lite0 All Masters 0x4008_0000 0x400F_EFFF Reserved 0x400F_F000 0x400F_FFFF Bitband region for general purpose input output GPIO All Masters 0x4010_0000 0x41FF...

Page 91: ...s 5 3 2 Peripheral Bridge 0 AIPS Lite 0 Memory Map Slots 0 79 are 32 bit data width modules Slots 80 95 are 16 bit data width modules and Slots 96 126 are 8 bit data width modules Table 5 2 Peripheral...

Page 92: ...orm 0x4002_0000 32 Flash memory FTMR 0x4002_1000 33 DMA_MUX channel multiplexor 0x4002_2000 34 0x4002_3000 35 0x4002_4000 36 FlexCAN0 0x4002_5000 37 FlexCAN1 0x4002_6000 38 FTM3 8 channel FlexTimer 0x...

Page 93: ...72 System Integration Module SIM 0x4004_9000 73 Port A mux control 0x4004_A000 74 Port B mux control 0x4004_B000 75 Port C mux control 0x4004_C000 76 Port D mux control 0x4004_D000 77 Port E mux cont...

Page 94: ...6_C000 108 0x4006_D000 109 0x4006_E000 110 0x4006_F000 111 0x4007_0000 112 0x4007_1000 113 0x4007_2000 114 0x4007_3000 115 CMP0 CMP1 CMP2 CMP3 0x4007_4000 116 0x4007_5000 117 0x4007_6000 118 0x4007_70...

Page 95: ...o edge placement module that requires both fast peripheral clock and PLL clock or PLL 2x clock The primary clocks for the system are generated from the MCGOUTCLK clock The clock generation circuitry p...

Page 96: ...CG CG CG CG Clock gate 32 kHz IRC PLL FLL MCGOUTCLK MCGPLLCLK MCG MCGFLLCLK 4 MHz IRC FRDIV CG FCRDIV PRDIV nano edge2x clock MCGPLL2XCLK OSCERCLK DIV OUTDIV2 CG fast peripheral clock Figure 6 1 Cloc...

Page 97: ...ammable from a divide by 1 through divide by 16 setting The following requirements must be met when configuring the clocks for this device 1 The System clock frequency that drives the CPU platform mus...

Page 98: ...ax High speed Run mode Frequency System CPU clock 120 MHz Fast Peripheral clock 120 MHz Bus Flash clock 24 MHz RUN mode Frequency System CPU clock 100 MHz Fast Peripheral clock 100 MHZ Bus Flash clock...

Page 99: ...st peripheral clocks are less than or equal to 4 tbd MHz and the bus flash clock is less than or equal to 1 MHz the nanoedge clock is disabled as it cannot support the nanoedge resolution for eFlexPWM...

Page 100: ...Core System clock Peripheral bridges Core System clock Bus clock Flash clock XBARA XBARB AOI Bus Flash clock LLWU PMC SIM RCM Bus Flash clock LPO Mode controller Bus Flash clock MCM Core System clock...

Page 101: ...AN Fast Peripheral clock OSCERCLK DSPI Fast Peripheral clock DSPI_SCK I2C Bus Flash clock I2C_SCL UART0 UART1 Fast Peripheral clock Human machine interfaces GPIO Core System clock 6 5 1 nano edge modu...

Page 102: ...enabled in all modes of operation including all low power modes This 1 kHz source is commonly referred to as LPO clock or 1 kHz LPO clock 6 5 5 PORT digital filter clocking The digital filters in the...

Page 103: ...clock must remain enabled if the LPTMRx is to continue operating in all required low power modes LPTMRx_PSR PCS LPTMRx prescaler glitch filter clock MCGIRCLK OSCERCLK ERCLK32K LPO Figure 6 5 LPTMRx pr...

Page 104: ...External clocks The input clocks to the SoC are described in detail in the MCG chapter FlexTimers The FlexTimers have an external clock input FTM_XCLK which must be no faster than 1 4 of the bus_clk f...

Page 105: ...configured for PSTOP2 only the core and system clocks are gated and the bus clock remains active The bus masters and bus slaves clocked by the system clock enter Stop mode but the bus slaves clocked...

Page 106: ...and internal power switches enabling the clock generators in the MCG enabling the system and bus clocks but not the core clock and negating the Stop mode signal to the bus masters and bus slaves The...

Page 107: ...o the SRAM and Flash read port but places all other bus masters and bus slaves into their stop mode Compute Operation can be enabled in either Run mode or VLP Run mode NOTE Do not enter any stop mode...

Page 108: ...eans the CPOACK bit is polled to determine when the AIPS peripheral space can be accessed without generating a bus error The DMA wakeup is also supported during Compute Operation and causes the CPOACK...

Page 109: ...p modes VLPS STOP are similar to ARM sleep deep mode The very low power run VLPR operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the applic...

Page 110: ...r CMP can be used NVIC is disabled LLWU is used to wake up SRAM_U and SRAM_L remain powered on content retained and I O states held Sleep Deep Wakeup Reset1 VLLS2 Very Low Leakage Stop2 Most periphera...

Page 111: ...Brown out Detection ON ON ON ON ON in VLLS1 2 3 optionally disabled in VLLS0 DMA static FF FF static OFF Watchdog FF FF FF FF OFF EWM static FF static static OFF Clocks 1kHz LPO ON ON ON ON ON in VLLS...

Page 112: ...bit cyclic ADCA B IRC4M only FF FF IRC4M only OFF CMPs 0 1 2 32 HS or LS level compare FF FF HS or LS level compare LS compare in VLLS1 2 3 OFF in VLLS0 6 bit DAC static FF FF static static OFF in VL...

Page 113: ...ntroller shut off clock sources and or the internal supplies driven from the on chip regulator as defined for the targeted low power mode In wait modes most of the system clocks are not affected by th...

Page 114: ...s The flash memory on this device should not be programmed or erased while operating in High Speed Run or VLPR power modes Flash Program Restrictions KV4x Reference Manual Rev 2 02 2015 114 Preliminar...

Page 115: ...d from the security byte of the flash configuration field NOTE The security features apply only to external accesses via debug CPU accesses to the flash are not affected by the status of FSEC In the u...

Page 116: ...sources of the MCU Boundary scan chain operations work but debugging capabilities are disabled so that the debug port cannot read flash contents Although most debug functions are disabled the debugger...

Page 117: ...the pinout and other available resources Four debug interfaces are supported IEEE 1149 1 JTAG IEEE 1149 7 JTAG cJTAG Serial Wire Debug SWD ARM Real Time Trace Interface The basic Cortex M4 debug arch...

Page 118: ...s JTAG AP Bridge to DFT BIST resources ROM Table Identifies which debug IP is available Core Debug Singlestep Register Access Run Core Status CoreSight Trace Funnel not shown in figure The CSTF combin...

Page 119: ...a match so providing hardware breakpoint capability TPIU Trace Port Inteface Unit Asynchronous Mode 1 pin TRACE_SWO available on JTAG_TDO MCM Miscellaneous Control Module The MCM provides miscellaneo...

Page 120: ...ntrol registers Through the ARM Debug Access Port DAP the debugger has access to the status and control elements implemented as registers on the DAP bus as shown in the following figure These register...

Page 121: ...AP SELECT 7 4 0x0 selects the bank with Status and Ctrl A 3 2 2 b00 selects the Status Register A 3 2 2 b01 selects the Control Register SELECT 7 4 0xF selects the bank with IDR A 3 2 2 b11 selects t...

Page 122: ...GREQ N Set to configure the system to be held in reset after the next recovery from a VLLSx mode This bit holds the in reset when VLLSx modes are exited to allow the debugger time to re initialize deb...

Page 123: ...Mass erase is enabled 6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled 0 Disabled 1 Enabled 7 LP Enabled Decode of LPLLSM control bits to indicate that VLPS LLS or...

Page 124: ...bug reset CDBGRSTREQ bit within the SWJ DP CTRL STAT register in the TCLK domain that allows the debugger to reset the debug logic TRST asserted via the cJTAG escape command System POR reset Conversel...

Page 125: ...ebugging to trace Operating System OS and application events and emits diagnostic system information The ITM emits trace information as packets There are four sources that can generate packets If mult...

Page 126: ...les are kept static or powered off the debugger cannot gather any debug data for the duration of the low power mode In the case that the debugger is held static the debug port returns to full function...

Page 127: ...he system frequency is limited but if a module does not have a limitation in its functionality it is still listed as FF static Module register states and associated memories are retained OFF Modules a...

Page 128: ...Debug Security KV4x Reference Manual Rev 2 02 2015 128 Preliminary Freescale Semiconductor Inc...

Page 129: ...bug reset JTAG reset nTRST reset Each of the system reset sources has an associated bit in the system reset status SRS registers See the Reset Control Module for register details The MCU can exit and...

Page 130: ...ocessor exits reset it performs the following Reads the start SP SP_main from vector table offset 0 Reads the start PC from vector table offset 4 LR is set to 0xFFFF_FFFF The on chip peripheral module...

Page 131: ...eup from VLLS The reset value for each filter defaults to off non detect The LPO filter is simple with a fixed filter value count of 3 There is also a synchronizer on the input signal that results in...

Page 132: ...s LLS mode exits via RESET pin and any VLLS mode exits via a wakeup or reset event the SRSL WAKEUP bit in mode controller module is set indicating the low leakage mode was active prior to the last sys...

Page 133: ...is the result of the core being locked because of an unrecoverable exception following the activation of the processor s built in system state protection hardware The LOCKUP condition causes a system...

Page 134: ...em reset 10 2 3 3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ DP CTRL STAT register to reset the debug modules However as explained below using the CDBGRSTREQ bit does not rese...

Page 135: ...t as shown in the following table Table 10 2 Flash Option Register Bit Definitions Bit Num Field Value Definition 7 6 Reserved Reserved for future expansion 5 FAST_INIT Select initialization speed on...

Page 136: ...eld in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the LVD The Mode Controller reset logic then controls a sequence to exit reset 1...

Page 137: ...NMI function is disabled in the NMI_DIS field the CPU begins execution at the PC location If the NMI input is low and the NMI function is enabled in the NMI_DIS field this results in an NMI interrupt...

Page 138: ...Boot KV4x Reference Manual Rev 2 02 2015 138 Preliminary Freescale Semiconductor Inc...

Page 139: ...pt module features 32 pin ports NOTE Not all pins are available on the device See the following section for details Each 32 pin port is assigned one interrupt Table 11 1 Ports summary Feature Port A P...

Page 140: ...rol Yes Yes Yes Yes Yes Pin mux at reset PTA0 PTA1 PTA2 PTA3 PTA4 ALT7 Others ALT0 ALT0 ALT0 ALT0 ALT0 Lock bit Yes Yes Yes Yes Yes Interrupt and DMA request Yes Yes Yes Yes Yes Digital glitch filter...

Page 141: ...fault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 126 B5 PTC19 DISABLED PTC19 UART3_CTS_ b ENET0_1588_ TMR3 FLEXPWMB_ B3 134 M10 VSS DISABLED VSS 135 F8 VDD DISABLED VDD 137 C9 PTD8 LLWU_P24 DISABLED PTD8...

Page 142: ...0 FTM1_CH0 UART0_TX 17 8 PTE21 ADCA_CH7b ADCA_CH7b PTE21 FTM1_CH1 UART0_RX 18 9 ADCA_CH2 ADCA_CH2 ADCA_CH2 19 10 ADCA_CH3 ADCA_CH3 ADCA_CH3 20 11 ADCA_CH6c ADCA_CH6c ADCA_CH6c 21 12 ADCA_CH7c ADCA_CH7...

Page 143: ...45 PTA15 CMP3_IN1 CMP3_IN1 PTA15 SPI0_SCK UART0_RX 46 PTA16 CMP3_IN2 CMP3_IN2 PTA16 SPI0_SOUT UART0_CTS_ b UART0_COL_ b 47 PTA17 ADCA_CH7e ADCA_CH7e PTA17 SPI0_SIN UART0_RTS_ b 48 30 VDD VDD VDD 49 31...

Page 144: ..._PCS3 UART1_RTS_ b FTM0_CH0 FLEXPWMA_ A3 XBAR0_IN11 71 104 B11 PTC1 LLWU_P6 ADCB_CH7b ADCB_CH7b PTC1 LLWU_P6 SPI0_PCS3 UART1_RTS_ b FTM0_CH0 FLEXPWMA_ A3 XBAR0_IN11 72 45 35 PTC2 ADCB_CH6c CMP1_IN0 AD...

Page 145: ...0 FTM3_CH6 82 115 C7 PTC10 ADCD_CH7d ADCD_CH7d PTC10 I2C1_SCL FTM3_CH6 FLEXPWMB_ A3 83 56 PTC11 LLWU_P11 ADCB_CH6e ADCB_CH6e PTC11 LLWU_P11 FTM3_CH7 83 116 B7 PTC11 LLWU_P11 ADCD_CH6e ADCD_CH6e PTC11...

Page 146: ...LLWU_P14 DISABLED PTD4 LLWU_P14 SPI0_PCS1 UART0_RTS_ b FTM0_CH4 FLEXPWMA_ A2 EWM_IN SPI0_PCS0 97 131 A4 PTD4 LLWU_P14 DISABLED PTD4 LLWU_P14 SPI0_PCS1 UART0_RTS_ b FTM0_CH4 FLEXPWMA_ A2 EWM_IN SPI1_PC...

Page 147: ...99 79 78 77 76 PTD6 LLWU_P15 PTD6 LLWU_P15 PTC7 PTC7 PTC6 LLWU_P10 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC5 LLWU_P9 PTC4 LLWU_P8 PTC4 LLWU_P8 50 49 48 47 46 45 44 43 42 41 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA1...

Page 148: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 PTD7 PTD6 LLWU_P15 PTD5 PTD4 LLWU_P14 PTD3 PTD2 LLWU_P13 PTD1 PTD0 LLWU_P12 PTC11 LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 LLWU_P8...

Page 149: ...LLWU_P8 36 35 34 33 PTC3 LLWU_P7 ADCB_CH6c CMP1_IN0 ADCB_CH7b ADCB_CH6b 32 31 30 29 28 27 26 25 PTB17 PTB16 ADCB_CH7e CMP3_IN5 ADCA_CH6e CMP2_IN2 ADCB_CH3 ADCB_CH2 RESET_b PTA19 PTA3 PTA2 PTA1 PTA0 24...

Page 150: ...Pinout diagrams KV4x Reference Manual Rev 2 02 2015 150 Preliminary Freescale Semiconductor Inc...

Page 151: ...specific device 12 2 1 Features The PORT module has the following features Pin interrupt Interrupt flag and enable registers for each pin Support for edge sensitive rising falling both or level sensi...

Page 152: ...bled GPIO and up to six chip specific digital functions Pad configuration fields are functional in all digital pin muxing modes 12 2 2 Modes of operation 12 2 2 1 Run mode In Run mode the PORT operate...

Page 153: ...ace detailed signal description Signal I O Description PORTx 31 0 I O External interrupt State meaning Asserted pin is logic 1 Negated pin is logic 0 Timing Assertion may occur at any time and can ass...

Page 154: ...5 1 160 4004_9044 Pin Control Register n PORTA_PCR17 32 R W See section 12 5 1 160 4004_9048 Pin Control Register n PORTA_PCR18 32 R W See section 12 5 1 160 4004_904C Pin Control Register n PORTA_PCR...

Page 155: ...38 Pin Control Register n PORTB_PCR14 32 R W See section 12 5 1 160 4004_A03C Pin Control Register n PORTB_PCR15 32 R W See section 12 5 1 160 4004_A040 Pin Control Register n PORTB_PCR16 32 R W See s...

Page 156: ...ee section 12 5 1 160 4004_B030 Pin Control Register n PORTC_PCR12 32 R W See section 12 5 1 160 4004_B034 Pin Control Register n PORTC_PCR13 32 R W See section 12 5 1 160 4004_B038 Pin Control Regist...

Page 157: ...Pin Control Register n PORTD_PCR9 32 R W See section 12 5 1 160 4004_C028 Pin Control Register n PORTD_PCR10 32 R W See section 12 5 1 160 4004_C02C Pin Control Register n PORTD_PCR11 32 R W See sect...

Page 158: ...004_D018 Pin Control Register n PORTE_PCR6 32 R W See section 12 5 1 160 4004_D01C Pin Control Register n PORTE_PCR7 32 R W See section 12 5 1 160 4004_D020 Pin Control Register n PORTE_PCR8 32 R W Se...

Page 159: ...ee section 12 5 1 160 4004_D07C Pin Control Register n PORTE_PCR31 32 R W See section 12 5 1 160 4004_D080 Global Pin Control Low Register PORTE_GPCLR 32 W always reads 0 0000_0000h 12 5 2 163 4004_D0...

Page 160: ...tions chapter for reset values per port DSE field Varies by port See the Signal Multiplexing and Signal Descriptions chapter for reset values per port PFE field Varies by port See Signal Multiplexing...

Page 161: ...10 Reserved 0111 Reserved 1000 ISF flag and Interrupt when logic 0 1001 ISF flag and Interrupt on rising edge 1010 ISF flag and Interrupt on falling edge 1011 ISF flag and Interrupt on either edge 110...

Page 162: ...igured as a digital input Refer to the device data sheet for filter characteristics 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 SRE Slew Rate Enable...

Page 163: ...bits 15 0 that are selected by GPWE 12 5 3 Global Pin Control High Register PORTx_GPCHR Only 32 bit writes are supported to this register Address Base address 84h offset Bit 31 30 29 28 27 26 25 24 2...

Page 164: ...flag will be cleared automatically at the completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a level sensitive...

Page 165: ...27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFCR field descriptions...

Page 166: ...ster PORT_PCRn associated with it The upper half of the Pin Control register configures the pin s capability to either interrupt the CPU or request a DMA transfer on a rising falling edge or both edge...

Page 167: ...menting an external pull resistor will ensure a pin does not float when its input buffer is enabled note that the internal pull resistor is automatically disabled whenever the output buffer is enabled...

Page 168: ...the interrupt status flag is set for any enabled DMA request in that port The DMA request negates after the DMA transfer is completed because that clears the interrupt status flags for all enabled DMA...

Page 169: ...r clock either the bus clock or the LPO clock If the synchronized input and the output of the digital filter remain different for a number of filter clock cycles equal to the filter width register con...

Page 170: ...Functional description KV4x Reference Manual Rev 2 02 2015 170 Preliminary Freescale Semiconductor Inc...

Page 171: ...clocking configuration System clock divide values Architectural clock gating control Flash and system RAM size configuration FlexTimer external clock hardware trigger and fault source selection UART0...

Page 172: ...h 13 2 7 185 4004_8024 System Device Identification Register SIM_SDID 32 R See section 13 2 8 186 4004_8034 System Clock Gating Control Register 4 SIM_SCGC4 32 R W F000_0030h 13 2 9 188 4004_8038 Syst...

Page 173: ..._7000h base 0h offset 4004_7000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 OSC32KSEL 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RAMSIZE 0 W Res...

Page 174: ...alue 0 13 2 2 System Options Register 2 SIM_SOPT2 SOPT2 contains the controls for selecting many of the module clock source options on this device See the Clock Distribution chapter for more informati...

Page 175: ...e clock select Selects the core system clock or MCG output clock MCGOUTCLK as the trace clock source 0 MCGOUTCLK 1 Core system clock 11 8 Reserved This field is reserved This read only field is reserv...

Page 176: ...ardware trigger 2 1 XBARA output 37 drives FTM3 hardware trigger 2 29 FTM3TRG1SRC FlexTimer 3 Hardware Trigger 1 Source Select Selects the source of FTM3 hardware trigger 1 0 PDB1 output trigger drive...

Page 177: ...s the source of FTM0 hardware trigger 1 0 PDB0 output trigger drives FTM0 hardware trigger 1 1 FTM1 channel match drives FTM0 hardware trigger 1 16 FTM0TRG0SRC FlexTimer 0 Hardware Trigger 0 Source Se...

Page 178: ...lt 2 must be configured for the FTM module fault function through the appropriate pin control register in the port control module 0 FTM0_FLT2 pin 1 CMP2 out 1 FTM0FLT1 FTM0 Fault 1 Select Selects the...

Page 179: ...C UART 1 receive data source select Selects the source for the UART 1 receive data 00 UART1_RX pin 01 CMP0 10 CMP1 11 Reserved 5 Reserved This field is reserved This read only field is reserved and al...

Page 180: ...ion 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 14 ADCBALTTRGEN ADCB alternate trigger enable Enable alternative conversion triggers for ADCB 0...

Page 181: ...is reserved and always has the value 0 ADCATRGSEL ADCA trigger select Selects the ADCA trigger source when alternative triggers are functional in stop and VLPS modes 0000 PDB external trigger pin inp...

Page 182: ...30 FTM3OCH6SRC FTM3 channel 6 output source 0 FTM3_CH6 pin is output of FTM3 channel 6 output 1 FTM3_CH6 pin is output of FTM3 channel 6 output modulated by carrier frequency clock as per FTM3CFSEL 29...

Page 183: ...M0CFSEL 21 FTM0OCH5SRC FTM0 channel 5 output source 0 FTM0_CH5 pin is output of FTM0 channel 5 output 1 FTM0_CH5 pin is output of FTM0 channel 5 output modulated by carrier frequency clock as per FTM0...

Page 184: ...the carrier signal for FTM0 Timer Modulation mode 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 FTM3SYNCBIT FTM3 Hardware Trigger 0 Software Synchr...

Page 185: ...1 FTM3 external clock driven by FTM_CLK1 pin 10 FTM3 external clock driven by FTM_CLK2 pin 11 Reserved 29 28 Reserved This field is reserved This read only field is reserved and always has the value 0...

Page 186: ...ture source select Selects the source for FTM1 channel 0 input capture NOTE When the FTM is not in input capture mode clear this field 00 FTM1_CH0 signal 01 CMP0 output 10 CMP1 output 11 Reserved Rese...

Page 187: ...s 0110 Kinetis V series 19 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 12 REVID Device revision number Specifies the silicon implementation number...

Page 188: ...escription 31 28 Reserved This field is reserved This read only field is reserved and always has the value 1 27 eFlexPWM3 eFlexPWM submodule 3 Clock Gate Control This bit controls the clock gate to th...

Page 189: ...RT0 UART0 Clock Gate Control This bit controls the clock gate to the UART0 module 0 Clock disabled 1 Clock enabled 9 7 Reserved This field is reserved This read only field is reserved and always has t...

Page 190: ...ADC ADC Clock Gate Control This bit controls the clock gate to the ADC module 0 Clock disabled 1 Clock enabled 27 AOI AOI Clock Gate Control This bit controls the clock gate to the AOI module 0 Clock...

Page 191: ...Control This bit controls the clock gate to the Port C module 0 Clock disabled 1 Clock enabled 10 PORTB Port B Clock Gate Control This bit controls the clock gate to the Port B module 0 Clock disabled...

Page 192: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SIM_SCGC6 field descriptions Field Description 31 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 FTM1 FTM1 Clock G...

Page 193: ...ols the clock gate to the SPI0 module 0 Clock disabled 1 Clock enabled 11 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 FTM3 FTM3 Clock Gate Control T...

Page 194: ...tion 31 9 Reserved This field is reserved This read only field is reserved and always has the value 0 8 DMA DMA Clock Gate Control This bit controls the clock gate to the DMA module 0 Clock disabled 1...

Page 195: ...T 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divi...

Page 196: ...it is loaded with either 0001 or 1111 depending on FTF_FOPT LPBOOT The flash clock frequency must be an integer divide of the system clock frequency 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3...

Page 197: ...eld is reserved This read only field is reserved and always has the value 1 27 24 PFSIZE Program flash size This field specifies the amount of program flash memory available on the device as set by IF...

Page 198: ...not need to be relocated out of Flash memory The wakeup time from Wait mode is extended when this bit is set 0 Flash remains enabled during Wait mode 1 Flash is disabled for the duration of Wait mode...

Page 199: ...High SIM_UIDH Address 4004_7000h base 1054h offset 4004_8054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W Reset x x x x x x x x x x x x x x x x x...

Page 200: ...field descriptions Field Description UID Unique Identification Unique identification for the device 13 2 19 Unique Identification Register Low SIM_UIDL Address 4004_7000h base 1060h offset 4004_8060h...

Page 201: ...Reserved This field is reserved This read only field is reserved and always has the value 0 3 1 TRACEDIV Trace clock divider divisor This field sets the divide value for the fractional clock divider u...

Page 202: ...nterval trigger 0 and PDB1 interval trigger 0 10 PDB0 interval trigger 0 11 PDB1 interval trigger 0 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 EW...

Page 203: ...lue 0 13 2 22 Miscellaneous Control Register 2 SIM_MISCTRL2 Address 4004_7000h base 1070h offset 4004_8070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SYNCCMP3SAMPL EWIN SYNCCMP2SAMPL EWI...

Page 204: ...0 Disable bypass synchronizer 1 Enable 20 SYNCCMP0SAMPLEWIN Synchronize XBARA s output for CMP0 s Sample Window Input with flash slow clock This field controls the synchronizer between XBARA s output...

Page 205: ...nto fast peripherials through xbar 0 Disable bypass synchronizer 1 Enable 10 SYNCXBARAPITTRIG2 Synchronize XBARA s Input PIT Trigger 2 with fast clock This field controls the synchronizer between PIT...

Page 206: ...is reserved This read only field is reserved and always has the value 0 1 WDOGCLKS WDOG Clock Select This write once bit selects the clock source of the WDOG2008 watchdog NOTE This is the choice of t...

Page 207: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SRPWRRDY SRPWRDETEN SR12STDBY 0 SR27STDBY SRPDN W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 SIM_PWRC field descriptions Field Description 31 26 Reserved This field is re...

Page 208: ...ge regulator 1 2 V supply placed in normal mode and SR12STDBY is write protected until chip reset 11 Nanoedge regulator 1 2 V supply placed in standby mode and SR12STDBY is write protected until chip...

Page 209: ...11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset 13 2 25 ADC Channel 6 7 Mux Control Register SIM_ADCOPT Address 4004_7000h base 1108h offset 4004_8108h Bi...

Page 210: ...annel to ADCB channel 7 000 ADCB MUX1 s channel a 001 ADCB MUX1 s channel b 010 ADCB MUX1 s channel c 011 ADCB MUX1 s channel d 100 ADCB MUX1 s channel e 101 ADCB MUX1 s channel f 110 ADCB MUX1 s chan...

Page 211: ...s the value 0 ADCACH6SEL ADCA MUX0 selection for ADCA channel 6 Selects ADCA MUX0 s channel to ADCA channel 6 000 ADCA MUX0 s channel a 001 ADCA MUX0 s channel b 010 ADCA MUX0 s channel c 011 ADCA MUX...

Page 212: ...Functional description KV4x Reference Manual Rev 2 02 2015 212 Preliminary Freescale Semiconductor Inc...

Page 213: ...nds sent by a master or host communicating on one of those ports The host master can be a firmware download application running on a PC or an embedded host communicating with the Kinetis Flashloader R...

Page 214: ...supported FlashEraseRegion Erase a range of sectors in flash Not supported WriteMemory Write data to memory Not supported ReadMemory Read data from memory Not supported FlashSecurityDisable Attempt t...

Page 215: ...tis Flashloader begins executing flashloader operations begin 1 The flashloader initializes the data and bss sections 2 All supported peripherals are initialized 3 The flashloader waits for communicat...

Page 216: ...te I2Cn entered interrupt state Ping packet received on UARTn Shutdown unused Peripherals Jump to user application Enter bootloader state machine No Yes Yes No No No No Yes No Yes Yes Yes Has Has Was...

Page 217: ...sponse command Commands may include an optional data phase If the data phase is incoming from host to flashloader then the data phase is part of the original command If the data phase is outgoing from...

Page 218: ...ing data phase The protocol for a command with an incoming data phase contains Command packet from host Generic response command packet to host Incoming data packets from host Generic response command...

Page 219: ...packets while it the host is waiting for the response to a command If the Generic Response packet prior to the start of the data phase does not have a status of kStatus_Success then the data phase is...

Page 220: ...ire operation 14 2 4 3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains Command packet from host ReadMemory Response command packet to host kCommandFlag...

Page 221: ...he data phase is really considered part of the response command The host may not send any further packets while it the host is waiting for the response to a command If the ReadMemory Response command...

Page 222: ...is packetized NOTE The term target refers to the Kinetis Flashloader device There are 6 types of packets used in the device Ping packet Ping Response packet Framing packet Command packet Data packet...

Page 223: ...coming Ping packet to determine the baud rate before replying with the Ping Response packet Once the Ping Response packet is received by the host the connection is established and the host starts send...

Page 224: ...Packet Format Byte Value Parameter 0 0x5A start byte 1 0xAn packetType The Packet Type field specifies the type of the packet from one of the defined types below Table 14 6 packetType Field packetTyp...

Page 225: ...mand packet carries a 32 bit command header and a list of 32 bit parameters Table 14 7 Command Packet Format Command Packet Format 32 bytes Command Header 4 bytes 28 bytes for Parameters Max 7 paramet...

Page 226: ...packets and data packets are embedded into framing packets for all of the transfers Table 14 9 Commands that are supported Command Name 0x01 FlashEraseAll 0x02 FlashEraseRegion 0x03 ReadMemory 0x04 W...

Page 227: ...n is determined by the last command sent from the host The data packet is also wrapped within a framing packet to ensure the correct packet data is received The contents of a data packet are simply th...

Page 228: ...e packet contains the framing packet data and the command packet data with the command response tag set to a GetPropertyResponse tag value 0xA7 The parameter count field in the header is set to greate...

Page 229: ...ch supported property has a unique 32 bit tag associated with it The tag occupies the first parameter of the command packet The target returns a GetPropertyResponse packet with the property values for...

Page 230: ...00001 CurrentVersion The GetProperty command has no data phase Response In response to a GetProperty command the target will send a GetPropertyResponse packet with the response tag set to 0xA7 The par...

Page 231: ...Kinetis Flashloader However the SetProperty command can only change the value of properties that are writable see Table 14 31 Properties used by Get SetProperty Commands If you try to set a value for...

Page 232: ...ketType_Command length 0x0C 0x00 crc16 0x67 0x8D Command packet commandTag 0x0C SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A VerifyWrites proper...

Page 233: ...n the commandTag field of the command packet The FlashEraseAll command requires no parameters Process command Host Target FlashEraseAll 0x5a a4 04 00c4 2e 01 00 00 00 0x5a a4 0c 00 53 63 a0 00 04 02 0...

Page 234: ...s not fit in the flash memory space the FlashEraseRegion command will fail and return kStatus_FlashAddressError 0x102 If any part of the region specified is protected the FlashEraseRegion command will...

Page 235: ...ory command while WriteMemory does have a data phase Table 14 23 Parameters for FillMemory Command Byte Command 0 3 Start address of memory to fill 4 7 Number of bytes to write with the pattern The st...

Page 236: ...quence for FillMemory Command Table 14 24 FillMemory Command Packet Format Example FillMemory Parameter Value Framing packet start byte 0x5A packetType 0xA4 kFramingPacketType_Command length 0x10 0x00...

Page 237: ...EraseRegion command Writing to flash requires the start address to be If the VerifyWrites property is set to true then writes to flash will also perform a flash verify program operation When writing t...

Page 238: ...Data Generic Response 0x5a a4 0c 00 23 72a0 00 00 02 00 00 00 00 04 00 00 00 ACK 0x5a a1 Figure 14 12 Protocol Sequence for WriteMemory Command Table 14 26 WriteMemory Command Packet Format Example Wr...

Page 239: ...7 Read memory command The ReadMemory command returns the contents of memory at the given address for a specified number of bytes This command can read any region of memory accessible by the CPU and no...

Page 240: ...ytes data 0x5a a5 length 16 CRC 16 32 bytes data ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 0x5a a4 0c 00 0e 23 a0 00 00 02 00 00 00 00 03 00 00 00 Figure 14 13 Command sequence for r...

Page 241: ...k pointer to the provided stack pointer address Prior to the jump the system is returned to the reset state The Jump address function argument pointer and stack pointer are the parameters required for...

Page 242: ...kFramingPacketType_Command length 0x04 0x00 crc16 0x6F 0x46 Command packet commandTag 0x0B reset flags 0x00 reserved 0x00 parameterCount 0x00 The Reset command has no data phase Response The target K...

Page 243: ...address and the direction bit is set as write An outgoing packet is read by the host with a selected I2C slave address and the direction bit is set as read 0x00 will be sent as the response to host i...

Page 244: ...han supported length Yes payload data from target No Set payload length to maximum supported length No No Reached maximum Report a timeout Yes End No 2 bytes Read 1 byte from target 0x5A received 0xA4...

Page 245: ...lid data The SPI bus configuration is Phase 1 data is sampled on rising edges Polarity 1 idle is high MSB is transmitted first For any transfer where the target does not have actual data to send the t...

Page 246: ...out payload data from target No Set payload length to maximum supported length No No maximum Report a timeout error End Yes End No 2 bytes 0x5A received 0xA4 received Reached retries Send 0x00 to shif...

Page 247: ...ore than 80 ms between bytes in a fixed UART transmission mode 8 bit data no parity bit and 1 stop bit If the bytes of the ping packet are sent one by one with more than 80 ms delay between them then...

Page 248: ...retries Figure 14 21 Host reads an ACK from target via UART Wait for ping response Yes Yes End Report Error No No Wait for 1 byte from target Wait for 1 byte from target 0x5A received 0xA7 received Wa...

Page 249: ...pported at 5 predefined speeds 125 kHz 250 kHz 500 kHz 750 kHz 1 MHz the default transfer rate The host application must use one of the 5 supported speeds for FlexCAN In Flashloader it supports automa...

Page 250: ...e host reads a ping packet ACK and response from the target Fetch ACK No Yes End No Process NAK Yes Report an error No Yes No Reached maximum Report a timeout error Yes 0x5A received 0xA2 received 0xA...

Page 251: ...urrentVersion No 01h 4 Current flashloader version AvailablePeripherals No 02h 4 The set of peripherals supported on this chip FlashStartAddress No 03h 4 Start address of program flash FlashSizeInByte...

Page 252: ...ystem Device Identification register FlashSecurityState No 11h 4 Indicates whether Flash security is enabled 0 Flash security is disabled 1 Flash security is enabled 14 4 1 Property Definitions Get Se...

Page 253: ...the lowest command tag value is 0x01 To get the bit mask for a given command use this expression mask 1 tag 1 Table 14 34 Command bits Bit 31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Command Reser...

Page 254: ..._SlaveTxUnderrun 300 SPI Slave TX Underrun error kStatus_SPI_SlaveRxOverrun 301 SPI Slave RX Overrun error kStatus_SPI_Timeout 302 SPI tranfser timed out kStatus_SPI_Busy 303 SPI instance is already b...

Page 255: ...rovide reset status information and reset filter control NOTE The RCM registers can be written only in supervisor mode Write accesses in user mode are blocked and will result in a bus error RCM memory...

Page 256: ...corresponding reset source caused the reset Address 4007_F000h base 0h offset 4007_F000h Bit 7 6 5 4 3 2 1 0 Read POR PIN WDOG 0 LOL LOC LVD WAKEUP Write Reset 1 0 0 0 0 0 1 0 RCM_SRS0 field descripti...

Page 257: ...s of external clock 1 Reset caused by a loss of external clock 1 LVD Low Voltage Detect Reset If PMC_LVDSC1 LVDRE is set and the supply drops below the LVD trip voltage an LVD reset occurs This field...

Page 258: ...ield is reserved This read only field is reserved and always has the value 0 3 MDM_AP MDM AP System Reset Request Indicates a reset has been caused by the host debugger system setting of the System Re...

Page 259: ...served and always has the value 0 2 RSTFLTSS Reset Pin Filter Select in Stop Mode Selects how the reset pin filter is enabled in Stop and VLPS modes and also during VLLS mode On exit from VLLS mode th...

Page 260: ...er count is 5 00101 Bus clock filter count is 6 00110 Bus clock filter count is 7 00111 Bus clock filter count is 8 01000 Bus clock filter count is 9 01001 Bus clock filter count is 10 01010 Bus clock...

Page 261: ...1c Reset 1 0 0 0 0 0 1 0 RCM_SSRS0 field descriptions Field Description 7 SPOR Sticky Power On Reset Indicates a reset has been caused by the power on detection logic Because the internal supply volta...

Page 262: ...etect Reset If PMC_LVDSC1 LVDRE is set and the supply drops below the LVD trip voltage an LVD reset occurs This field is also set by POR 0 Reset not caused by LVD trip or POR 1 Reset caused by LVD tri...

Page 263: ...st Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM AP Control Register 0 Reset not caused by host debugger system setting of the System...

Page 264: ...Reset memory map and register descriptions KV4x Reference Manual Rev 2 02 2015 264 Preliminary Freescale Semiconductor Inc...

Page 265: ...de and the functionality available while in each of the modes The SMC is able to function during even the deepest low power modes See AN4503 Power Management for Kinetis and ColdFire MCUs for further...

Page 266: ...operation for the device The following table describes the power modes available for the device Table 16 1 Power modes Mode Description RUN The MCU can be run at full speed and the internal supply is...

Page 267: ...System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid The MCU is placed in a low leakage mode by powering down the intern...

Page 268: ...ormal RUN mode and AVLP is 0 an attempt to enter VLPR mode using PMCTRL RUNM is blocked and PMCTRL RUNM remains 00b indicating the MCU is still in Normal Run mode NOTE This register is reset on Chip R...

Page 269: ...bit allows the MCU to enter any very low leakage stop mode VLLSx 0 Any VLLSx mode is not allowed 1 Any VLLSx mode is allowed 0 Reserved This field is reserved This read only field is reserved and alwa...

Page 270: ...ured during the previous stop mode entry sequence preventing the system from entering that mode This field is cleared by hardware at the beginning of any stop mode entry sequence and is set if the seq...

Page 271: ...consumption In PSTOP2 only system clocks are gated allowing peripherals running on bus clock to remain fully functional In PSTOP1 both system and bus clocks are gated 00 STOP Normal Stop mode 01 PSTOP...

Page 272: ...es that trigger Chip POR not VLLS It is unaffected by reset types that do not trigger Chip POR not VLLS See the Reset section details for more information Address 4007_E000h base 3h offset 4007_E003h...

Page 273: ...er mode is VLLS 1000_0000 Current power mode is HSRUN 16 4 Functional description 16 4 1 Power mode transitions The following figure shows the power mode state transitions available on the chip Any re...

Page 274: ...s figure Table 16 7 Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Register...

Page 275: ...OTE If VLPS was entered directly from RUN transition 7 hardware forces exit back to RUN and does not allow a transition to VLPR 7 RUN VLPS Sleep now or sleep on exit modes entered with SLEEPDEEP set w...

Page 276: ...to enter Stop mode 3 After all masters have acknowledged they are ready to enter Stop mode requests are made to all bus slaves to enter Stop mode 4 After all slaves have acknowledged they are ready t...

Page 277: ...disabled in these configurations 16 4 2 5 Transition from stop modes to Debug mode The debugger module supports a transition from STOP WAIT VLPS and VLPW back to a Halted state when the debugger has b...

Page 278: ...which frequencies are supported Mode protection must be set to allow VLP modes that is PMPROT AVLP is 1 PMCTRL RUNM must be set to 10b to enter VLPR Flash programming erasing is not allowed NOTE Do n...

Page 279: ...r should be polled to determine when the system has completed entry into HSRUN mode To reenter normal RUN mode clear RUNM Any reset will also clear RUNM and cause the system to exit to normal RUN mode...

Page 280: ...modes to meet your application needs The stop modes range from a stopped CPU with all I O logic and memory states retained and certain asynchronous mode peripherals operating to a powered down CPU wi...

Page 281: ...in which VLPS mode can be entered are listed here Entry into stop via the sleep now or sleep on exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in VLPR...

Page 282: ...upt In the LLWU interrupt service routine ISR the user can poll the LLWU module wake up flags to determine the source of the wake up When entering VLLS each I O pin is latched as configured before exe...

Page 283: ...ols and settings to be powered off To give time to the debugger to sync with the MCU the MDM AP Control Register includes a Very Low Leakage Debug Request VLLDBGREQ bit that is set to configure the Re...

Page 284: ...Functional description KV4x Reference Manual Rev 2 02 2015 284 Preliminary Freescale Semiconductor Inc...

Page 285: ...mory map and register descriptions below describe the registers using byte addresses MCM memory map Absolute address hex Register name Width in bits Access Reset value Section page E008_0008 Crossbar...

Page 286: ...to AXBS input port n is absent 1 A bus slave connection to AXBS input port n is present 17 2 2 Crossbar Switch AXBS Master Configuration MCM_PLAMC PLAMC is a 16 bit read only register identifying the...

Page 287: ...0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 MCM_CR field descriptions Field Description 31 Reserved This field is reserved This...

Page 288: ...s to SRAM_U array generates a bus error 25 24 SRAMUAP SRAM_U arbitration priority Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_U array 00 Round...

Page 289: ...0 MCM_ISR field descriptions Field Description 31 FIDCE FPU input denormal interrupt enable 0 Disable interrupt 1 Enable interrupt 30 29 Reserved This field is reserved This read only field is reserv...

Page 290: ...rocessor s FPU Once set this bit remains set until software clears the FPSCR IXC bit 0 No interrupt 1 Interrupt occurred 11 FUFC FPU underflow interrupt status This read only bit is a copy of the core...

Page 291: ...is field is reserved This read only field is reserved and always has the value 0 17 2 5 Compute Operation Control Register MCM_CPO This register controls the Compute Operation Address E008_0000h base...

Page 292: ...t has not completed 0 CPOREQ Compute Operation request This bit is auto cleared by vector fetching if CPOWOI 1 0 Request is cleared 1 Request Compute Operation 17 3 Functional description This section...

Page 293: ...FIXCE and a number is inexact FIXC FPU underflow interrupt is enabled FUFCE and an underflow occurs FUFC FPU overflow interrupt is enabled FOFCE and an overflow occurs FOFC FPU divide by zero interrup...

Page 294: ...Functional description KV4x Reference Manual Rev 2 02 2015 294 Preliminary Freescale Semiconductor Inc...

Page 295: ...nt 18 3 Low voltage detect LVD system This device includes a system to guard against low voltage conditions This protects memory contents and controls MCU system states during supply voltage variation...

Page 296: ...t until the supply voltage rises above this threshold The LVD field in the SRS register of the RCM module RCM_SRS LVD is set following an LVD or power on reset 18 3 2 LVD interrupt operation By config...

Page 297: ...ypes Each register s description provides details For more information about the types of reset on this chip refer to the Reset section details The PMC registers can be written only in supervisor mode...

Page 298: ...The register s other bits are reset on Chip Reset Not VLLS For more information about these reset types refer to the Reset section details Address 4007_D000h base 0h offset 4007_D000h Bit 7 6 5 4 3 2...

Page 299: ...ontrol 2 register PMC_LVDSC2 This register contains status and control bits to support the low voltage warning function While the device is in the very low power or low leakage modes the LVD system is...

Page 300: ...rved This field is reserved This read only field is reserved and always has the value 0 LVWV Low Voltage Warning Voltage Select Selects the LVW trip point voltage VLVW The actual voltage for the warni...

Page 301: ...ates whether certain peripherals and the I O pads are in a latched state as a result of having been in a VLLS mode Writing 1 to this field when it is set releases the I O pads and certain peripherals...

Page 302: ...d descriptions continued Field Description 0 Bandgap buffer not enabled 1 Bandgap buffer enabled Memory map and register descriptions KV4x Reference Manual Rev 2 02 2015 302 Preliminary Freescale Semi...

Page 303: ...able 19 1 Wakeup sources for LLWU inputs Input Wakeup source Input Wakeup source LLWU_P0 PTE1 LLWU_P0 pin LLWU_P12 PTD0 LLWU_P12 pin LLWU_P1 PTE2 LLWU_P1 pin LLWU_P13 PTD2 LLWU_P13 pin LLWU_P2 PTE4 LL...

Page 304: ...ls on using the LLWU 19 2 1 Features The LLWU module features include Support for up to 32 external input pins and up to 8 internal modules with individual enable bits for MCU interrupt from low leaka...

Page 305: ...edge event will be detected by the LLWU 19 2 2 3 Debug mode When the chip is in Debug mode and then enters a VLLSx mode no debug logic works in the fully functional low leakage mode Upon an exit from...

Page 306: ...ion details LLWU memory map Absolute address hex Register name Width in bits Access Reset value Section page 4007_C000 LLWU Pin Enable 1 register LLWU_PE1 8 R W 00h 19 4 1 307 4007_C001 LLWU Pin Enabl...

Page 307: ...00h base 0h offset 4007_C000h Bit 7 6 5 4 3 2 1 0 Read WUPE3 WUPE2 WUPE1 WUPE0 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE1 field descriptions Field Description 7 6 WUPE3 Wakeup Pin Enable For LLWU_P3 Enables...

Page 308: ...p input pins LLWU_P7 LLWU_P4 NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS It is unaffected by reset types that do not trigger Chip Reset not V...

Page 309: ...n enabled with falling edge detection 11 External input pin enabled with any change detection 19 4 3 LLWU Pin Enable 3 register LLWU_PE3 LLWU_PE3 contains the field to enable and select the edge detec...

Page 310: ...enabled with any change detection WUPE8 Wakeup Pin Enable For LLWU_P8 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin...

Page 311: ...led as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection WUPE12 Wa...

Page 312: ...up Pin Enable For LLWU_P17 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 Exter...

Page 313: ...enabled with falling edge detection 11 External input pin enabled with any change detection 3 2 WUPE21 Wakeup Pin Enable For LLWU_P21 Enables and configures the edge detection for the wakeup pin 00 E...

Page 314: ...tection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External...

Page 315: ...nput pin enabled with any change detection 5 4 WUPE30 Wakeup Pin Enable For LLWU_P30 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 Exte...

Page 316: ...Reset 0 0 0 0 0 0 0 0 LLWU_ME field descriptions Field Description 7 WUME7 Wakeup Module Enable For Module 7 Enables an internal module as a wakeup source input 0 Internal module flag not used as wak...

Page 317: ...eup Module Enable For Module 0 Enables an internal module as a wakeup source input 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 19 4 10 LLWU Pin Flag 1...

Page 318: ...r mode To clear the flag write a one to WUF5 0 LLWU_P5 input was not a wakeup source 1 LLWU_P5 input was a wakeup source 4 WUF4 Wakeup Flag For LLWU_P4 Indicates that an enabled external wakeup pin wa...

Page 319: ...d by a write of a 1 to the corresponding WUFx bit The wakeup flag WUFx if set will remain set if the associated WUPEx bit is cleared NOTE This register is reset on Chip Reset not VLLS and by reset typ...

Page 320: ...at an enabled external wakeup pin was a source of exiting a low leakage power mode To clear the flag write a one to WUF11 0 LLWU_P11 input was not a wakeup source 1 LLWU_P11 input was a wakeup source...

Page 321: ...set 0 0 0 0 0 0 0 0 LLWU_PF3 field descriptions Field Description 7 WUF23 Wakeup Flag For LLWU_P23 Indicates that an enabled external wakeup pin was a source of exiting a low leakage power mode To cle...

Page 322: ...the flag write a one to WUF17 0 LLWU_P17 input was not a wakeup source 1 LLWU_P17 input was a wakeup source 0 WUF16 Wakeup Flag For LLWU_P16 Indicates that an enabled external wakeup pin was a source...

Page 323: ...e To clear the flag write a one to WUF29 0 LLWU_P29 input was not a wakeup source 1 LLWU_P29 input was a wakeup source 4 WUF28 Wakeup Flag For LLWU_P28 Indicates that an enabled external wakeup pin wa...

Page 324: ...kage power mode such as a real time clock module or CMP module the flag from the associated peripheral is accessible as the MWUFx bit The flag will need to be cleared in the peripheral instead of writ...

Page 325: ...Indicates that an enabled internal peripheral was a source of exiting a low leakage power mode To clear the flag follow the internal peripheral flag clearing mechanism 0 Module 3 input was not a wake...

Page 326: ...Description 7 FILTF Filter Detect Flag Indicates that the filtered external wakeup pin selected by FILTSEL was a source of exiting a low leakage power mode To clear the flag write a one to FILTF 0 Pi...

Page 327: ...cription 7 FILTF Filter Detect Flag Indicates that the filtered external wakeup pin selected by FILTSEL was a source of exiting a low leakage power mode To clear the flag write a one to FILTF 0 Pin Fi...

Page 328: ...s of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled Four wakeup detect filters are available for selected external pins Glitch filte...

Page 329: ...least five LPO clock cycles before entering VLLSx mode to allow the filter to initialize NOTE After recovering from a VLLS mode user must restore chip configuration before clearing PMC_REGSC ACKISO I...

Page 330: ...Functional description KV4x Reference Manual Rev 2 02 2015 330 Preliminary Freescale Semiconductor Inc...

Page 331: ...d in the chip Crossbar Switch Slave Modules Master Modules M2 M0 M1 S0 S3 ARM core code bus ARM core system bus DMA Flash controller S1 SRAM controller_L S2 Mux Peripheral bridge 0 GPIO controller SRA...

Page 332: ...found here provides information on the layout configuration and programming of the crossbar switch The crossbar switch connects bus masters and bus slaves using a crossbar switch structure This struct...

Page 333: ...ter simply sees wait states inserted until the targeted slave port can service the master s request The latency in servicing the request depends on each master s priority level and the responding slav...

Page 334: ...to use the slave port This is done to save the initial clock of arbitration delay that otherwise would be seen if the same master had to arbitrate to gain control of the slave port If present the flas...

Page 335: ...ased on the requesting master port Table 20 1 How the Crossbar Switch grants control of a slave port to a master When Then the Crossbar Switch grants control to the requesting master Both of the follo...

Page 336: ...last master of the slave port was master 1 and master 0 4 and 5 make simultaneous requests they are serviced in the order 4 then 5 then 0 The round robin arbitration mode generally provides a more fa...

Page 337: ...each assigned to a PACRx field within the PACRA PACRP registers However fewer peripherals are supported on this device See Peripheral Memory Map for details of the peripheral slot assignments for this...

Page 338: ...e are modules which contain a programming model of control and status registers The system masters read and write these registers through the peripheral bridge The peripheral bridge performs a bus pro...

Page 339: ...See section 21 6 3 347 4000_004C Peripheral Access Control Register AIPS_PACRH 32 R W See section 21 6 3 347 4000_0050 Peripheral Access Control Register AIPS_PACRI 32 R W See section 21 6 3 347 4000...

Page 340: ...served This read only field is reserved and always has the value 0 30 MTR0 Master 0 Trusted For Read Determines whether the master is trusted for read accesses 0 This master is not trusted for read ac...

Page 341: ...value 0 22 MTR2 Master 2 Trusted For Read Determines whether the master is trusted for read accesses 0 This master is not trusted for read accesses 1 This master is trusted for read accesses 21 MTW2...

Page 342: ...R41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PA...

Page 343: ...ipheral allows write accesss When this bit is set and a write access is attempted access terminates with an error response and no peripheral access initiates 0 This peripheral allows write accesses 1...

Page 344: ...peripheral requires supervisor privilege level for accesses 21 WP2 Write Protect Determines whether the peripheral allows write accesss When this bit is set and a write access is attempted access ter...

Page 345: ...eral requires supervisor privilege level for accesses 13 WP4 Write Protect Determines whether the peripheral allows write accesss When this bit is set and a write access is attempted access terminates...

Page 346: ...ipheral requires supervisor privilege level for accesses 5 WP6 Write Protect Determines whether the peripheral allows write accesses When this field is set and a write access is attempted access termi...

Page 347: ...hese registers Address 4000_0000h base 40h offset 4d i where i 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SP0 WP0 TP0 0 SP1 WP1 TP1 0 SP2 WP2 TP2 0 SP3 WP3 TP3 W Reset 0 0 0 0 0...

Page 348: ...with an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for accesses...

Page 349: ...ith an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for accesses 1...

Page 350: ...with an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for accesses...

Page 351: ...t the master privilege level must indicate the supervisor access attribute and the MPRx MPLn control field for the master must be set If not access terminates with an error response and no peripheral...

Page 352: ...1 Access support All combinations of access size and peripheral data port width are supported An access that is larger than the target peripheral s data width will be decomposed to multiple smaller a...

Page 353: ...ive 3 UART0 Transmit Transmit 4 UART1 Recieve Receive 5 UART1 Transmit Transmit 6 flexPWM_WR0 Submodule 0 DMA request to update PWM buffers 7 flexPWM_WR1 Submodule 1 DMA request to update PWM buffers...

Page 354: ...eceive Receive 17 SPI0 transmit Transmit 18 XBARA_OUT0 19 XBARA_OUT1 20 XBARA_OUT2 21 XBARA_OUT3 22 I2C0 23 24 FTM0 Ch0 Channel 0 25 FTM0 Ch1 Channel 1 26 FTM0 Ch2 Channel 2 27 FTM0 Ch3 Channel 3 28 F...

Page 355: ...enabled 61 DMAX MUX always enabled 62 DMAX MUX always enabled 63 DMAX MUX always enabled 22 1 2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first four DMA channels T...

Page 356: ...x always on slots can be routed to 16 channels 16 independently selectable DMA channel routers The first two channels additionally provide a trigger functionality Each channel router can be assigned t...

Page 357: ...has no external pins 22 4 Memory map register definition This section provides a detailed description of all memory mapped registers in the DMAMUX DMAMUX memory map Absolute address hex Register name...

Page 358: ...ots peripheral slots or always on slots in the system NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior This is true even if a channel is disabled...

Page 359: ...ionally the DMAMUX channels may be divided into two classes Channels that implement the normal routing functionality plus periodic triggering capability Channels that implement only the normal routing...

Page 360: ...been seen This is illustrated in the following figure DMA request Peripheral request Trigger Figure 22 20 DMAMUX channel triggering normal operation After the DMA request has been serviced the periphe...

Page 361: ...od to periodically read data from external devices and transfer the results into memory without processor intervention Using the GPIO ports to drive or sample waveforms By configuring the DMA to trans...

Page 362: ...software should initiate the start of a DMA transfer an always enabled DMA source can be used to provide maximum flexibility When activating a DMA channel via software subsequent executions of the mi...

Page 363: ...se 22 6 2 Enabling and configuring sources To enable a source with periodic triggering 1 Determine with which DMA channel the source will be associated Note that only the first 2 DMA channels have per...

Page 364: ...ng the channel 3 Write 0x85 to CHCFG1 base address 0x01 The following code example illustrates steps 1 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example...

Page 365: ...e illustrates steps 2 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits volatile unsigned char CHCFG0 volatile unsigned char DMAM...

Page 366: ...In File main c include registers h CHCFG8 0x00 CHCFG8 0x87 Initialization application information KV4x Reference Manual Rev 2 02 2015 366 Preliminary Freescale Semiconductor Inc...

Page 367: ...rocessor The hardware microarchitecture includes A DMA engine that performs Source and destination address calculations Data movement operations Local memory containing transfer control descriptors fo...

Page 368: ...channels provide the same functionality This structure allows data transfers associated with one channel to be preempted after the completion of a read write sequence if a higher priority channel acti...

Page 369: ...al the eDMA engine performs a series of source read destination write operations until the number of bytes specified in the minor loop byte count has moved For descriptors where the sizes are not equa...

Page 370: ...ware initiation Initiation via a channel to channel linking mechanism for continuous transfers Peripheral paced hardware requests one per channel Fixed priority and round robin channel arbitration Cha...

Page 371: ...continues operation until the channel retires Wait Before entering Wait mode the DMA attempts to complete its current transfer After the transfer completes the device enters Wait mode 23 3 Memory map...

Page 372: ...he value of zero Writes to reserved bits in a register are ignored Reading or writing a reserved memory location generates a bus error DMA memory map Absolute address hex Register name Width in bits A...

Page 373: ...8 R W See section 23 3 17 410 4000_8104 Channel n Priority Register DMA_DCHPRI7 8 R W See section 23 3 17 410 4000_8105 Channel n Priority Register DMA_DCHPRI6 8 R W See section 23 3 17 410 4000_8106...

Page 374: ...nk Major Loop Count Channel Linking Disabled DMA_TCD0_BITER_ELINKNO 16 R W Undefined 23 3 32 424 4000_9020 TCD Source Address DMA_TCD1_SADDR 32 R W Undefined 23 3 18 411 4000_9024 TCD Signed Source Ad...

Page 375: ...ed DMA_TCD2_CITER_ELINKYES 16 R W Undefined 23 3 27 418 4000_9056 DMA_TCD2_CITER_ELINKNO 16 R W Undefined 23 3 28 419 4000_9058 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCD2_...

Page 376: ...4 4000_9088 TCD Signed Minor Loop Offset Minor Loop and Offset Enabled DMA_TCD4_NBYTES_MLOFFYES 32 R W Undefined 23 3 23 415 4000_908C TCD Last Source Address Adjustment DMA_TCD4_SLAST 32 R W Undefine...

Page 377: ...DMA_TCD6_SADDR 32 R W Undefined 23 3 18 411 4000_90C4 TCD Signed Source Address Offset DMA_TCD6_SOFF 16 R W Undefined 23 3 19 411 4000_90C6 TCD Transfer Attributes DMA_TCD6_ATTR 16 R W Undefined 23 3...

Page 378: ...atter Gather Address DMA_TCD7_DLASTSGA 32 R W Undefined 23 3 29 420 4000_90FC TCD Control and Status DMA_TCD7_CSR 16 R W Undefined 23 3 30 421 4000_90FE TCD Beginning Minor Loop Link Major Loop Count...

Page 379: ...A_TCD9_DADDR 32 R W Undefined 23 3 25 417 4000_9134 TCD Signed Destination Address Offset DMA_TCD9_DOFF 16 R W Undefined 23 3 26 417 4000_9136 TCD Current Minor Loop Link Major Loop Count Channel Link...

Page 380: ...Undefined 23 3 20 412 4000_9168 TCD Minor Byte Count Minor Loop Disabled DMA_TCD11_NBYTES_MLNO 32 R W Undefined 23 3 21 413 4000_9168 TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disable...

Page 381: ...12_CSR 16 R W Undefined 23 3 30 421 4000_919E TCD Beginning Minor Loop Link Major Loop Count Channel Linking Enabled DMA_TCD12_BITER_ELINKYES 16 R W Undefined 23 3 31 423 4000_919E TCD Beginning Minor...

Page 382: ...416 4000_91D0 TCD Destination Address DMA_TCD14_DADDR 32 R W Undefined 23 3 25 417 4000_91D4 TCD Signed Destination Address Offset DMA_TCD14_DOFF 16 R W Undefined 23 3 26 417 4000_91D6 TCD Current Mi...

Page 383: ...unt Channel Linking Disabled DMA_TCD15_BITER_ELINKNO 16 R W Undefined 23 3 32 424 23 3 1 Control Register DMA_CR The CR defines the basic operating configuration of the DMA Arbitration can be configur...

Page 384: ...ed the NBYTES field is a 30 bit vector When minor loop mapping is disabled EMLM is 0 all 32 bits of TCDn word2 are assigned to the NBYTES field Address 4000_8000h base 0h offset 4000_8000h Bit 31 30 2...

Page 385: ...eved by simply increasing the NBYTES value A larger NBYTES value provides more efficient faster processing 0 A minor loop channel link made to itself goes through channel arbitration before being acti...

Page 386: ...Field Description 31 VLD Logical OR of all ERR status bits 0 No ERR bits are set 1 At least one ERR bit is set indicating a valid error exists that has not been cleared 30 17 Reserved This field is r...

Page 387: ...was a configuration error detected in the TCDn_DOFF field TCDn_DOFF is inconsistent with TCDn_ATTR DSIZE 3 NCE NBYTES CITER Configuration Error 0 No NBYTES CITER configuration error 1 The last recorde...

Page 388: ...19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ERQ15 ERQ14 ERQ13 ERQ12 ERQ11 ERQ10 ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0 W Reset 0 0 0...

Page 389: ...est signal for the corresponding channel is enabled 6 ERQ6 Enable DMA Request 6 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channe...

Page 390: ...flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller Address 4000_8000h base 14h offset 4000_8014h Bit 31 30 29 28 27 26 25 24 23 22 21...

Page 391: ...or interrupt request 8 EEI8 Enable Error Interrupt 8 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel gen...

Page 392: ...able the error interrupt for a given channel The data value on a register write causes the corresponding bit in the EEI to be cleared Setting the CAEE bit provides a global clear function forcing the...

Page 393: ...a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 19h offset 4000_8019h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAEE 0 SEEI Reset 0 0 0 0 0 0 0 0 DMA_SEEI field descript...

Page 394: ...ite multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Ah offset 4000_801Ah Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAER 0 CERQ Reset 0 0 0 0 0...

Page 395: ...s as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Bh offset 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMA_SERQ field desc...

Page 396: ...s a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Ch offset 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMA_CDNE field descrip...

Page 397: ...this register return all zeroes Address 4000_8000h base 1Dh offset 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMA_SSRT field descriptions Field Description...

Page 398: ...te multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Eh offset 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0 0 0 0 0...

Page 399: ...ite multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Fh offset 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset 0 0 0 0 0...

Page 400: ...INT a 1 in any bit position clears the corresponding channel s interrupt request A zero in any bit position has no affect on the corresponding channel s current interrupt status The CINT register is p...

Page 401: ...e interrupt request for corresponding channel is active 9 INT9 Interrupt Request 9 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is act...

Page 402: ...routed to the interrupt controller During the execution of the interrupt service routine associated with any DMA errors it is software s responsibility to clear the appropriate bit negating the error...

Page 403: ...not occurred 1 An error in this channel has occurred 14 ERR14 Error In Channel 14 0 An error in this channel has not occurred 1 An error in this channel has occurred 13 ERR13 Error In Channel 13 0 An...

Page 404: ...n this channel has not occurred 1 An error in this channel has occurred 4 ERR4 Error In Channel 4 0 An error in this channel has not occurred 1 An error in this channel has occurred 3 ERR3 Error In Ch...

Page 405: ...this status is affected by the ERQ bits Address 4000_8000h base 34h offset 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 1...

Page 406: ...ed for the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by hardware 0 A hardware service request for...

Page 407: ...for channel 6 is not present 1 A hardware service request for channel 6 is present 5 HRS5 Hardware Request Status Channel 5 The HRS bit for its respective channel remains asserted for the period when...

Page 408: ...respective channel remains asserted for the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by hardware...

Page 409: ...or channel 10 1 Enable asynchronous DMA request for channel 10 9 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 0 Disable asynchronous DMA request for channel 9 1 Enable asynchrono...

Page 410: ...rbitration is enabled CR ERCA 0 the contents of these registers define the unique priorities associated with each channel The channel priorities are evaluated by numeric value for example 0 is the low...

Page 411: ...ource Address DMA_TCDn_SADDR Address 4000_8000h base 1000h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SADDR W Reset x x...

Page 412: ...circular data queue easily For data queues requiring power of 2 size bytes the queue should start at a 0 modulo size address and the SMOD field should be set to the appropriate value for the queue fre...

Page 413: ...x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset DMA_TCDn_NBYTES_MLNO field descriptions Field Description NBYTES Minor Byte Transfer Count Number of bytes to...

Page 414: ...00_8000h base 1008h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE NBYTES W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 415: ...p Offset Minor Loop and Offset Enabled DMA_TCDn_NBYTES_MLOFFYES One of three registers this register TCD_NBYTES_MLNO or TCD_NBYTES_MLOFFNO defines the number of bytes to transfer per request Which reg...

Page 416: ...nt has transferred This is an indivisible operation and cannot be halted It can however be stalled by using the bandwidth control field or via preemption After the minor count is exhausted the SADDR a...

Page 417: ...e destination data 23 3 26 TCD Signed Destination Address Offset DMA_TCDn_DOFF Address 4000_8000h base 1014h offset 32d i where i 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DOFF Write Re...

Page 418: ...NK channel linking NOTE This bit must be equal to the BITER ELINK bit otherwise a configuration error is reported 0 The channel to channel linking is disabled 1 The channel to channel linking is enabl...

Page 419: ...bles linking to another channel defined by the LINKCH field The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specified chan...

Page 420: ...x x x x x x x x x Notes x Undefined at reset DMA_TCDn_DLASTSGA field descriptions Field Description DLASTSGA Destination last address adjustment or the memory address for the next transfer control des...

Page 421: ...ast write of each minor loop This behavior is a side effect of reducing start up latency 00 No eDMA engine stalls 01 Reserved 10 eDMA engine stalls for 4 cycles after each R W 11 eDMA engine stalls fo...

Page 422: ...ther format The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution 3 DREQ Disable Request If this flag is set the eDMA...

Page 423: ...y BITER LINKCH The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specified channel If channel linking disables the BITER val...

Page 424: ...the TCDn_BITER ELINK bit is cleared the TCDn_BITER register is defined as follows Address 4000_8000h base 101Eh offset 32d i where i 0d to 15d Bit 15 14 13 12 11 10 9 8 Read ELINK BITER Write Reset x...

Page 425: ...qual to the corresponding CITER field otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field is reloaded into the CITER field If the channel i...

Page 426: ...he control module then into the program model and channel arbitration In the next cycle the channel arbitration performs using the fixed priority or round robin algorithm After arbitration is complete...

Page 427: ...continues until the minor byte count has transferred After the minor byte count has moved the final phase of the basic data flow is performed In this segment the address path logic performs the requi...

Page 428: ...tting in the transfer control descriptor or an illegal priority register setting in Fixed Arbitration mode or An error termination to a bus master read or write cycle A configuration error is reported...

Page 429: ...he scatter gather address DLAST_SGA is not aligned on a 32 byte boundary If minor loop channel linking is enabled upon channel completion a configuration error is reported when the link is attempted i...

Page 430: ...ansfer in the event the full data transfer is no longer needed The cancel transfer bit does not abort the channel It simply stops the transferring of data and then retires the channel through its norm...

Page 431: ...lows for a pool of low priority large data moving channels to be defined These low priority channels can be configured to not preempt each other thus preventing a low priority channel from consuming t...

Page 432: ...ransfers occur at the core s datapath width For all transfers involving the internal peripheral bus 32 bit transfer sizes are used In all cases the transfer rate includes the time to read the source p...

Page 433: ...write 12 13 This cycle represents the data phase of the last destination write 13 14 The eDMA engine completes the execution of the inner minor loop and prepares to write back the required TCDn field...

Page 434: ...bus read data phase write_ws Wait states seen during the system bus write data phase exit Channel shutdown 3 cycles 23 4 4 3 eDMA performance example Consider a system with the following characteristi...

Page 435: ...ing is absorbed in or overlaps the previous executing channel Note When channel linking or scatter gather is enabled a two cycle delay is imposed on the next channel selection and startup This allows...

Page 436: ...es such as interrupts major loop channel linking and scatter gather operations if enabled Table 23 297 TCD Control and Status fields TCDn_CSR field name Description START Control bit to start channel...

Page 437: ...added to current address after each transfer often the same value as xSIZE Each DMA source S and destination D has its own Address xADDR Size xSIZE Offset xOFF Modulo xMOD Last Address Adjustment xLAS...

Page 438: ...iderations for the eDMA 23 5 3 1 Fixed channel arbitration In this mode the channel service request from the highest priority channel is selected to execute 23 5 3 2 Round robin channel arbitration Ch...

Page 439: ...TCDn_CSR START bit requests channel service 2 The channel is selected by arbitration for servicing 3 eDMA engine writes TCDn_CSR DONE 0 TCDn_CSR START 0 TCDn_CSR ACTIVE 1 4 eDMA engine reads channel...

Page 440: ...AST 32 TCDn_DLAST_SGA 32 This would generate the following sequence of events 1 First hardware that is eDMA peripheral request for channel service 2 The channel is selected by arbitration for servicin...

Page 441: ...sfers are executed as follows a Read byte from location 0x1010 read byte from location 0x1011 read byte from 0x1012 read byte from 0x1013 b Write 32 bits to location 0x2010 first iteration of the mino...

Page 442: ...ircular buffer is created where the address wraps to the original value while the 28 upper address bits 0x1234567x retain their original value In this example the source address is set to 0x12345670 t...

Page 443: ...model The TCD status bits execute the following sequence for a hardware activated channel Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware peripheral request as...

Page 444: ...imultaneously in the global TCD map a higher priority channel is actively preempting a lower priority channel 23 5 6 Channel Linking Channel linking or chaining is a mechanism where one channel sets t...

Page 445: ...e summarizes how a DMA channel can link to another DMA channel i e use another channel s TCD at the end of a loop Table 23 299 Channel Linking Parameters Desired Link Behavior TCD Control Field Name D...

Page 446: ...uld be set in the programmer s model but it would be unclear whether the actual link was made before the channel retired The following coherency model is recommended when executing a dynamic channel l...

Page 447: ...e major linkch field and the e_sg bit with a single read For both dynamic channel linking and scatter gather requests the TCD local memory controller forces the TCD major e_link and TCD e_sg bits to z...

Page 448: ...jor loop channel linking For a channel using major loop channel linking the coherency model described here may be used for a dynamic scatter gather request This method uses the TCD dlast_sga field as...

Page 449: ...sga changed the dynamic link attempt was successful the new TCD s e_sg value cleared the e_sg bit Chapter 23 Direct Memory Access Controller eDMA KV4x Reference Manual Rev 2 02 2015 Freescale Semicond...

Page 450: ...Initialization application information KV4x Reference Manual Rev 2 02 2015 450 Preliminary Freescale Semiconductor Inc...

Page 451: ...the EWM low power modes and the corresponding chip low power modes Table 24 2 EWM low power modes Module mode Chip mode Wait Wait VLPW Stop Stop VLPS 24 1 3 EWM_OUT pin state in low power modes When...

Page 452: ...the internal watchdog in that it does not reset the MCU s CPU and peripherals The EWM if allowed to time out provides an independent EWM_out pin that when asserted resets or places an external circuit...

Page 453: ...the following if the EWM enters the stop mode during CPU service mechanism At the exit from stop mode by an interrupt refresh mechanism state machine starts from the previous state which means if firs...

Page 454: ...s The EWM has two external signals as shown in the following table Table 24 3 EWM Signal Descriptions Signal Description I O EWM_in EWM input for safety status of external safety circuits The polarity...

Page 455: ...escriptions Field Description 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 INTEN Interrupt Enable This bit when set and EWM_out is asserted an inte...

Page 456: ...hin a fixed number of peripheral bus cycles of the first data byte This fixed number of cycles is called EWM_service_time 24 4 3 Compare Low Register EWM_CMPL The CMPL register is reset to zero after...

Page 457: ...unaway code from changing this field software should write to this field after a CPU reset even if the default maximum service time is required 24 5 Functional Description The following sections descr...

Page 458: ...ster When the EWM_out pin is asserted it can only be deasserted by forcing a MCU reset Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset 24 5 2 The...

Page 459: ...eset occurs The EWM compare registers are used to create a service window which is used by the CPU to service refresh the EWM module If the CPU services the EWM when the counter value lies between CMP...

Page 460: ...ue reaches CMPH prior to a unique EWM service The counter value reaches the CMPH value and no service of the EWM resets the counter to zero and assert the EWM_out pin irrespective of the EWM_in pin Th...

Page 461: ...ock Chip clock LPO Oscillator 1 kHz LPO Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 25 1 2 WDOG low power modes This table shows the WDOG low power modes and the corresponding chip low...

Page 462: ...endent from CPU bus clock Choice between two clock sources Low power oscillator LPO External system clock Unlock sequence for allowing updates to write once WDOG control configuration bits All WDOG co...

Page 463: ...fresh outside window leads to reset Robust refresh mechanism Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus clock cycles Count of WDOG resets as they occur Configurable inter...

Page 464: ...esh Seq No config after unlocking No unlock after reset 0xB480 0xA602 System Bus Clock 32 bit Modulus Reg Time out Value DebugEN Window_begin WDOGTEST STOPEN WAITEN WDOGT WDOG CLKSRC WINEN WDOGEN WDOG...

Page 465: ...G_UNLOCK 2 Wait one bus clock cycle You cannot update registers on the bus clock cycle immediately following the write of the unlock sequence 3 An update window equal in length to the watchdog configu...

Page 466: ...er words you must write at least the first word of the unlocking sequence within the WCT after reset After this is done you have a further 20 bus clock cycles the maximum allowed gap between the words...

Page 467: ...r This is known as refreshing the watchdog within a window of the total time out period If a refresh is attempted before the timer reaches the window value the watchdog generates a reset or interrupt...

Page 468: ...resumes its operation from the point of pausing The entry of the system into the debug mode does not excuse it from compulsorily configuring the watchdog in the WCT time after unlock unless the system...

Page 469: ...it to put the watchdog in the functional test mode Setting this bit automatically switches the watchdog timer to a fast clock source The switching of the clock source is done to achieve a faster time...

Page 470: ...ronous counter followed by combinational logic that generates an overflow signal The overflow signal acts as an enable to the N 1th stage In the test mode when an individual byte N is tested byte N 1...

Page 471: ...registers within the WCT window after unlocking At least one of the following registers must be written to within the WCT window to avoid reset WDOG_ST_CTRL_H WDOG_ST_CTRL_L WDOG_TO_VAL_H WDOG_TO_VAL...

Page 472: ...tchdog Time out Value Register Low WDOG_TOVALL 16 R W 4B4Ch 25 8 4 475 4005_2008 Watchdog Window Register High WDOG_WINH 16 R W 0000h 25 8 5 476 4005_200A Watchdog Window Register Low WDOG_WINL 16 R W...

Page 473: ...dog in the functional test mode In this mode the watchdog timer and the associated compare and reset generation logic is tested for correct operation The clock for the timer is switched from the main...

Page 474: ...of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled 0 WDOG is disabled 1 WDOG is enabled 25 8 2 Watchdog Status and Control Register Low WDOG_STCTRLL Addr...

Page 475: ..._TOVALL The time out value of the watchdog must be set to a minimum of four watchdog clock cycles This is to take into account the delay in new settings taking effect in the watchdog clock domain Addr...

Page 476: ...terrupts and then resets the system 25 8 6 Watchdog Window Register Low WDOG_WINL NOTE You must set the Window Register value lower than the Time out Value Register Address 4005_2000h base Ah offset 4...

Page 477: ...descriptions Field Description WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write once registers writable again The required unlock sequence is 0xC520 followed...

Page 478: ...watchdog timer 25 8 11 Watchdog Reset Count register WDOG_RSTCNT Address 4005_2000h base 14h offset 4005_2014h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read RSTCNT Write Reset 0 0 0 0 0 0 0 0 0 0 0 0...

Page 479: ...unlock registers For an 8 bit access to these registers writing a correct value requires at least two bus clock cycles resulting in an invalid value in the registers for one cycle Therefore the system...

Page 480: ...ite2 and write4 It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged The difference for 8 bit accesses is that the criterion for detectin...

Page 481: ...effect in the watchdog clock domain You must take care not only to refresh the watchdog within the watchdog timer s actual time out period but also provide enough allowance for the time it takes for t...

Page 482: ...due to synchronization The same holds true for an exit from the stop mode this time resulting in a two to three watchdog clock cycle delay in the timer restarting In case the duration of the stop mode...

Page 483: ...XB_IN5 XBARA_IN6 XB_IN6 XBARA_IN7 XB_IN7 XBARA_IN8 XB_IN8 XBARA_IN9 XB_IN9 XBARA_IN10 XB_IN10 XBARA_IN11 XB_IN11 XBARA_IN12 CMP0_OUT XBARA_IN13 CMP1_OUT XBARA_IN14 CMP2_OUT XBARA_IN15 CMP3_OUT XBARA_I...

Page 484: ...1 DMA ch7_done1 XBARA_IN42 PIT ch0 XBARA_IN43 PIT ch1 XBARA_IN44 XBARA_IN45 ENC_CMP POS_MATCH XBARA_IN46 AND_OR_INVERT_0 XBARA_IN47 AND_OR_INVERT_1 XBARA_IN48 AND_OR_INVERT_2 XBARA_IN49 AND_OR_INVERT_...

Page 485: ..._OUT19 CMP3 window sample input XBARA_OUT20 PWMA0_EXTA XBARA_OUT21 PWMA1_EXTA XBARA_OUT22 PWMA2_EXTA XBARA_OUT23 PWMA3_EXTA XBARA_OUT24 PWMA0_EXT_SYNC XBARA_OUT25 PWMA1_EXT_SYNC XBARA_OUT26 PWMA2_EXT_...

Page 486: ...ent select field The intended application of this module is to provide a flexible crossbar switch function that allows any input typically from external GPIO or internal module outputs to be connected...

Page 487: ...PBus interface for select and control fields Register write protection input signal 26 2 3 Modes of Operation The XBAR module design operates in only a single mode of operation Functional Mode The var...

Page 488: ..._REQ 0 DMA_REQ 1 INT_REQ 1 DMA_REQ M 1 INT_REQ M 1 edge status edge selection and interrupt DMA generation controls Figure 26 1 XBAR Block Diagram 26 3 Signal Descriptions The following table summariz...

Page 489: ...ut s DMA_REQ n is a DMA request to the DMA controller 26 3 4 DMA_ACK n DMA Acknowledge Input s DMA_ACK n is a DMA acknowledge input from the DMA controller 26 3 5 INT_REQ n Interrupt Request Output s...

Page 490: ...10 XBARA_SEL10 16 R W 0000h 26 4 11 496 4005_9016 Crossbar A Select Register 11 XBARA_SEL11 16 R W 0000h 26 4 12 496 4005_9018 Crossbar A Select Register 12 XBARA_SEL12 16 R W 0000h 26 4 13 497 4005_9...

Page 491: ...to XBARA_OUT1 refer to Functional Description section for input output assignment 7 6 Reserved This field is reserved This read only field is reserved and always has the value 0 SEL0 Input XBARA_INn t...

Page 492: ...nment 7 6 Reserved This field is reserved This read only field is reserved and always has the value 0 SEL4 Input XBARA_INn to be muxed to XBARA_OUT4 refer to Functional Description section for input o...

Page 493: ...0 SEL8 Input XBARA_INn to be muxed to XBARA_OUT8 refer to Functional Description section for input output assignment 26 4 6 Crossbar A Select Register 5 XBARA_SEL5 Address 4005_9000h base Ah offset 4...

Page 494: ...ption section for input output assignment 26 4 8 Crossbar A Select Register 7 XBARA_SEL7 Address 4005_9000h base Eh offset 4005_900Eh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL15 0 SEL14 Wri...

Page 495: ...ction for input output assignment 26 4 10 Crossbar A Select Register 9 XBARA_SEL9 Address 4005_9000h base 12h offset 4005_9012h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL19 0 SEL18 Write Res...

Page 496: ...ption section for input output assignment 26 4 12 Crossbar A Select Register 11 XBARA_SEL11 Address 4005_9000h base 16h offset 4005_9016h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL23 0 SEL22...

Page 497: ...ction for input output assignment 26 4 14 Crossbar A Select Register 13 XBARA_SEL13 Address 4005_9000h base 1Ah offset 4005_901Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL27 0 SEL26 Write R...

Page 498: ...ption section for input output assignment 26 4 16 Crossbar A Select Register 15 XBARA_SEL15 Address 4005_9000h base 1Eh offset 4005_901Eh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL31 0 SEL30...

Page 499: ...ction for input output assignment 26 4 18 Crossbar A Select Register 17 XBARA_SEL17 Address 4005_9000h base 22h offset 4005_9022h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL35 0 SEL34 Write R...

Page 500: ...ption section for input output assignment 26 4 20 Crossbar A Select Register 19 XBARA_SEL19 Address 4005_9000h base 26h offset 4005_9026h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL39 0 SEL38...

Page 501: ...ction for input output assignment 26 4 22 Crossbar A Select Register 21 XBARA_SEL21 Address 4005_9000h base 2Ah offset 4005_902Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL43 0 SEL42 Write R...

Page 502: ...ption section for input output assignment 26 4 24 Crossbar A Select Register 23 XBARA_SEL23 Address 4005_9000h base 2Eh offset 4005_902Eh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL47 0 SEL46...

Page 503: ...ction for input output assignment 26 4 26 Crossbar A Select Register 25 XBARA_SEL25 Address 4005_9000h base 32h offset 4005_9032h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL51 0 SEL50 Write R...

Page 504: ...ption section for input output assignment 26 4 28 Crossbar A Select Register 27 XBARA_SEL27 Address 4005_9000h base 36h offset 4005_9036h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 SEL55 0 SEL54...

Page 505: ...Description section for input output assignment 26 4 30 Crossbar A Select Register 29 XBARA_SEL29 Address 4005_9000h base 3Ah offset 4005_903Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 SE...

Page 506: ...This bit reflects the results of edge detection for XBAR_OUT1 This field is set to 1 when an edge consistent with the current setting of EDGE1 is detected on XBAR_OUT1 This field is cleared by writing...

Page 507: ...no effect When interrupt or DMA functionality is enabled for XBAR_OUT0 this field is 1 when the interrupt or DMA request is asserted and 0 when the interrupt or DMA request has been cleared 0 Active e...

Page 508: ...2 IEN2 DEN2 Write w1c Reset 0 0 0 0 0 0 0 0 XBARA_CTRL1 field descriptions Field Description 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 STS3 E...

Page 509: ...sabled 1 DMA enabled 7 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 STS2 Edge detection status for XBAR_OUT2 This bit reflects the results of edge de...

Page 510: ...Ln The SELn select values are configured in the XBAR_SEL registers All muxes share the same inputs in the same order A subset of XBAR_OUT outputs has dedicated control fields in a Crossbar Control XBA...

Page 511: ...lue of STSn Thus the DMA request asserts when the edge specified by EDGEn is detected on XBAR_OUT n Also a rising edge on DMA_ACK n sets STSn to zero and thus clears the DMA request When DEN is 0 DMA_...

Page 512: ...Interrupts and DMA Requests KV4x Reference Manual Rev 2 02 2015 512 Preliminary Freescale Semiconductor Inc...

Page 513: ...M3_CH_allTRIG XBARB_IN7 FTM3_INIT XBARB_IN8 PWMA0_TRG0 PWMA0_TRIG1 XBARB_IN9 PWMA1_TRG0 PWMA1_TRG1 XBARB_IN10 PWMA2_TRG0 PWMA2_TRG1 XBARB_IN11 PWMA3_TRG0 PWMA3_TRG1 XBARB_IN12 PDB0_OUT XBARB_IN13 ADCA...

Page 514: ...0 XBARB_OUT1 AOI_IN1 XBARB_OUT2 AOI_IN2 XBARB_OUT3 AOI_IN3 XBARB_OUT4 AOI_IN4 XBARB_OUT5 AOI_IN5 XBARB_OUT6 AOI_IN6 XBARB_OUT7 AOI_IN7 XBARB_OUT8 AOI_IN8 XBARB_OUT9 AOI_IN9 XBARB_OUT10 AOI_IN10 XBARB_...

Page 515: ...Chip Configuration details XBARB memory map Absolute address hex Register name Width in bits Access Reset value Section page 4005_A000 Crossbar B Select Register 0 XBARB_SEL0 16 R W 0000h 27 3 1 515...

Page 516: ...15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 8 SEL3 Input XBARB_INn to be muxed to XBARB_OUT3 refer to Functional Description section for input...

Page 517: ...ut XBARB_INn to be muxed to XBARB_OUT7 refer to Functional Description section for input output assignment 7 5 Reserved This field is reserved This read only field is reserved and always has the value...

Page 518: ...ment 7 5 Reserved This field is reserved This read only field is reserved and always has the value 0 SEL10 Input XBARB_INn to be muxed to XBARB_OUT10 refer to Functional Description section for input...

Page 519: ...scriptions Field Description 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 8 SEL15 Input XBARB_INn to be muxed to XBARB_OUT15 refer to Functional...

Page 520: ...Memory Map and Register Descriptions KV4x Reference Manual Rev 2 02 2015 520 Preliminary Freescale Semiconductor Inc...

Page 521: ...utput Assigned Input AOI_IN0 XBARB_OUT0 AOI_IN1 XBARB_OUT1 AOI_IN2 XBARB_OUT2 AND_OR_INVERT_0 XBARA_IN46 AOI_IN3 XBARB_OUT3 AOI_IN4 XBARB_OUT4 AOI_IN5 XBARB_OUT5 AND_OR_INVERT_1 XBARA_IN47 AOI_IN6 XBA...

Page 522: ...cators from a variety of device modules and generating event output signals that can be routed to an inter peripheral crossbar switch or other peripherals Its programming model is accessed through the...

Page 523: ...put D Event PT0_AC PT1_AC PT2_AC PT3_AC PT0_BC PT0_CC PT0_DC PT1_BC PT1_CC PT1_DC PT2_BC PT2_CC PT2_DC PT3_BC PT3_CC PT3_DC Figure 28 1 Simplified AOI Block Diagram Chapter 28 Crossbar AND OR INVERT A...

Page 524: ...d by the selected event inputs and outputs Additionally as a memory mapped device located on the slave peripheral bus it responds based strictly on memory address for accesses to its programming model...

Page 525: ...uct termuses 8 bits of configuration information 2 bits for each of the four selected event inputs The resulting logic provides a simple yet powerful Boolean function evaluation for defining an event...

Page 526: ...duct term 11 Force the B input in this product term to a logical one 11 10 PT0_CC Product term 0 C input configuration This 2 bit field defines the Boolean evaluation associated with the selected inpu...

Page 527: ...fines the Boolean evaluation associated with the selected input D in product term 1 00 Force the D input in this product term to a logical zero 01 Pass the D input in this product term 10 Complement t...

Page 528: ...ct term 3 A input configuration This 2 bit field defines the Boolean evaluation associated with the selected input A in product term 3 00 Force the A input in this product term to a logical zero 01 Pa...

Page 529: ...A typical application of the AOI module is to be integrated with one or more inter peripheral crossbar switch modules as illustrated in the following figure The 20 external inputs are shared by two cr...

Page 530: ...model configuration for simple boolean expressions The AOI module provides a universal boolean function generator using a four term sum of products expression with each product term containing true o...

Page 531: ...t term 3 PT3_BC 0 B PT3_BC 1 B PT3_CC 0 C PT3_CC 1 C PT3_DC 0 D PT3_DC 1 D where the bits of the combined BFECRT01n BFCRT23n registers correspond to the PT 0 3 _ A B C D C 1 0 terms in the equation Co...

Page 532: ...nation function of its four dedicated inputs An Bn Cn and Dn Propagation through the AOI and any associated inter peripheral crossbar switch modules is intended to be single bus clock cycle Functional...

Page 533: ...atic Gain Control AGC to optimize power consumption in high frequency ranges 3 8 MHz 8 32 MHz using low power mode High gain option in frequency ranges 32 kHz 3 8 MHz and 8 32 MHz Voltage and frequenc...

Page 534: ...he external reference clock source in this MCU The figure found here shows the block diagram of the OSC module XTAL EXTAL XTL_CLK Mux 4096 Counter OSC Clock Enable STOP OSCERCLK_UNDIV ERCLKEN OSCCLK R...

Page 535: ...able shows all possible connections Table 29 2 External Caystal Resonator Connections Oscillator Mode Connections Low frequency 32 kHz low power Connection 11 Low frequency 32 kHz high gain Connection...

Page 536: ...P bits OSC VSS Cx Cy RF Crystal or Resonator XTAL EXTAL Figure 29 4 Crystal Ceramic Resonator Connections Connection 3 29 6 External Clock Connections In external clock mode the pins can be connected...

Page 537: ...age 4006_5000 OSC Control Register OSC_CR 8 R W 00h 29 7 1 1 537 4006_5002 OSC_DIV OSC_OSC_DIV 8 R W 00h 29 7 1 2 539 29 7 1 1 OSC Control Register OSC_CR NOTE After OSC is enabled and starts generati...

Page 538: ...erved This field is reserved This read only field is reserved and always has the value 0 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load 0 Disable the selection 1 Add 2...

Page 539: ...This read only field is reserved and always has the value 0 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 Reserved This field is reserved This read on...

Page 540: ...ts 29 8 1 1 Off The OSC enters the Off state when the system does not require OSC clocks Upon entering this state XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by c...

Page 541: ...CLK_OUT Its frequency is determined by the external components being used 29 8 1 4 External Clock mode The OSC enters external clock state when it is enabled and external reference clock selection bit...

Page 542: ...l capacitors could be used 29 8 2 2 Low Frequency Low Power Mode In low frequency low power mode the oscillator uses a gain control loop to minimize power consumption As the oscillation amplitude incr...

Page 543: ...age filtering and converts the output to logic levels 29 8 3 Counter The oscillator output clock OSC_CLK_OUT is gated off until the counter has detected 4096 cycles of its input clock XTL_CLK After 40...

Page 544: ...hese bits are set the OSC is in operation After waking up from Very Low Leakage Stop VLLSx modes all OSC register bits are reset and initialization is required through software 29 11 Interrupts The OS...

Page 545: ...an external crystal ceramic resonator or another external clock source to produce the external reference clock 30 1 1 Features Key features of the MCG module are Frequency locked loop FLL Digitally co...

Page 546: ...eference low power oscillator clock generators are provided HGO RANGE EREFS External clock from the Crystal Oscillator Can be used as a source for the FLL and or the PLL Can be selected as the clock s...

Page 547: ...ipherals MCG Internal Reference Clock MCGIRCLK is provided as a clock source for other on chip peripherals This figure presents the block diagram of the MCG module Chapter 30 Multipurpose Clock Genera...

Page 548: ...V0 LOLIE0 Sync Auto Trim Machine IRCST PLLST CLKST ATMS SCTRIM SCFTRIM FCTRIM ATMST IREFSTEN OSCINIT0 EREFS0 HGO0 RANGE0 External DRS Clock Valid Peripheral BUSCLK PLLCLKEN0 IRCSCLK IRCS CLKS CLKS DCO...

Page 549: ...1 Register MCG_C1 8 R W 04h 30 3 1 550 4006_4001 MCG Control 2 Register MCG_C2 8 R W 80h 30 3 2 551 4006_4002 MCG Control 3 Register MCG_C3 8 R W Undefined 30 3 3 552 4006_4003 MCG Control 4 Register...

Page 550: ...E 0 Divide Factor is 4 for all other RANGE values Divide Factor is 128 011 If RANGE 0 Divide Factor is 8 for all other RANGE values Divide Factor is 256 100 If RANGE 0 Divide Factor is 16 for all othe...

Page 551: ...illator OSC chapter for more details and the device data sheet for the frequency ranges used 00 Encoding 0 Low frequency range selected for the crystal oscillator 01 Encoding 1 High frequency range se...

Page 552: ...eference clock frequency by controlling the slow internal reference clock period The SCTRIM bits are binary weighted that is bit 1 adjusts twice as much as bit 0 Increasing the binary value increases...

Page 553: ...0 25 MHz 1 32 768 kHz 732 24 MHz 01 0 31 25 39 0625 kHz 1280 40 50 MHz 1 32 768 kHz 1464 48 MHz 10 0 31 25 39 0625 kHz 1920 60 75 MHz 1 32 768 kHz 2197 72 MHz 11 0 31 25 39 0625 kHz 2560 80 100 MHz 1...

Page 554: ...le memory location to this bit 1 A value for FCTRIM is loaded during reset from a factory programmed location 2 A value for SCFTRIM is loaded during reset from a factory programmed location 30 3 5 MCG...

Page 555: ...PLL0 The resulting frequency must be in the range of 8 MHz to 16 MHz After the PLL0 is enabled by setting either PLLCLKEN0 or PLLS the PRDIV0 value must not be changed when LOCK0 is zero Table 30 7 PL...

Page 556: ...value of the RANGE0 bits in the C2 register should not be changed CME0 bit should be set to a logic 0 before the MCG enters any Stop mode Otherwise a reset request may occur while in Stop mode CME0 s...

Page 557: ...in the C5 register or the VDIV 4 0 bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock Loss of PLL reference clock will also cause the LOCK...

Page 558: ...to internal synchronization between clock domains The IRCST bit will only be updated if the internal reference clock is enabled either by the MCG being in a mode that uses the IRC or by setting the C...

Page 559: ...o the new clock mode switch Otherwise FLL filter and frequency values will change 0 FLL filter and FLL frequency will reset on changes to currect clock mode 1 Fll filter and FLL frequency retain their...

Page 560: ...Value Low Register MCG_ATCVL Address 4006_4000h base Bh offset 4006_400Bh Bit 7 6 5 4 3 2 1 0 Read ATCVL Write Reset 0 0 0 0 0 0 0 0 MCG_ATCVL field descriptions Field Description ATCVL ATM Compare Va...

Page 561: ...n a PLL loss of lock indication 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 1 Reserved This field is reserved This read only field is reserved and a...

Page 562: ...PBE clock mode and the C1 CLKS and S CLKST will automatically be set to 2 b10 If entering Normal Stop mode when the MCG is in PEE mode with PLLSTEN 0 the MCG will reset to PBE clock mode and C1 CLKS a...

Page 563: ...tion for more details In FEE mode the PLL is disabled in a low power state unless C5 PLLCLKEN is set FLL Bypassed Internal FBI FLL bypassed internal FBI mode is entered when all the following conditio...

Page 564: ...when all the following conditions occur 10 is written to C1 CLKS 0 is written to C1 IREFS 1 is written to C6 PLLS 0 is written to C2 LP In PBE mode MCGOUTCLK is derived from the external reference clo...

Page 565: ...to 2 b10 and S LOCK bit will clear without setting S LOLS If C5 PLLSTEN 1 the S LOCK bit will not get cleared and on exit the MCG will continue to run in PEE mode 1 Caution If entering VLPR mode MCG...

Page 566: ...ce Clock MCGIRCLK provides a clock source for other on chip peripherals and is enabled when C1 IRCLKEN 1 When enabled MCGIRCLK is driven by either the fast internal reference clock 4 MHz IRC which can...

Page 567: ...he PLL LOCK status bit is cleared 30 4 5 MCG Fixed Frequency Clock The MCG Fixed Frequency Clock MCGFFCLK provides a fixed frequency clock source for other on chip peripherals see the block diagram Th...

Page 568: ...reference clock such as FBE clock mode The MCG must not be configured in a clock mode where selected IRC ATM clock is used to generate the system clock The bus clock is also required to be running wit...

Page 569: ...lock in tfll_acquire milliseconds 30 5 1 1 Initializing the MCG Because the MCG comes out of reset in FEI mode the only MCG modes that can be directly switched to upon reset are FEE FBE and FBI modes...

Page 570: ...zed If in FEE mode check to make sure S IREFST is cleared before moving on If in FBE mode check to make sure S IREFST is cleared and S CLKST bits have changed to 2 b10 indicating the external referenc...

Page 571: ...z 5 Wait for the FLL lock time to guarantee FLL is running at new C4 DRST_DRS and C4 DMX32 programmed frequency To change from FEI clock mode to FBI clock mode follow this procedure 1 Change C1 CLKS b...

Page 572: ...NIT must be checked before moving on in the application software Additionally care must be taken to ensure that the reference clock divider C1 FRDIV and C5 PRDIV0 is set properly for the mode being sw...

Page 573: ...clock source less than 8 MHz the MCG must not be configured for any of the PLL modes PEE and PBE 30 5 3 1 Example 1 Moving from FEI to PEE Mode with OSC0 as the source for the external crystal clock...

Page 574: ...a BLPE If a transition through BLPE mode is desired first set C2 LP to 1 b BLPE PBE C6 0x4E C6 PLLS set to 1 selects the PLL At this time with a C1 PRDIV value of 2 b001 the PLL reference divider is...

Page 575: ...C1 0x20 C1 CLKS set to 2 b00 to select the output of the PLL as the system clock source b Loop until S CLKST are 2 b11 indicating that the PLL output is selected to feed MCGOUTCLK in the current clock...

Page 576: ...MODE C2 0x2E C2 LP 1 CHECK CHECK C1 0x20 CHECK CONTINUE IN PEE MODE S PLLST 1 S LOCK0 1 S CLKST 10 S CLKST 11 S LP 1 S IREFST 0 S OSCINIT0 1 C5 0x01 C5 VDIV0 1 Figure 30 14 Flowchart of FEI to PEE mod...

Page 577: ...ed first set C2 LP to 1 b BLPE FBE C6 0x00 C6 PLLS clear to 0 to select the FLL At this time with C1 FRDIV value of 3 b100 the FLL divider is set to 512 resulting in a reference frequency of 16 MHz 51...

Page 578: ...ed as the reference clock source c Loop until S CLKST are 2 b01 indicating that the internal reference clock is selected to feed MCGOUTCLK 4 Lastly FBI transitions into BLPI mode a C2 0x22 C2 LP is 1...

Page 579: ...FST 0 CHECK S CLKST 01 YES NO YES C2 LP 1 C6 0x00 IN BLPE MODE IN BLPE MODE NO YES C2 0x2C C2 LP 0 C2 0x2E ENTER BLPE MODE C2 LP 1 Figure 30 15 Flowchart of PEE to BLPI mode transition using an 16 MHz...

Page 580: ...Initialization Application information KV4x Reference Manual Rev 2 02 2015 580 Preliminary Freescale Semiconductor Inc...

Page 581: ...ns Flash memory type Read Write Program flash memory 8 bit 16 bit and 32 bit reads 1 1 A write operation to program flash memory results in a bus error In addition for bank 0 the FMC provides three se...

Page 582: ...ck per way Single entry buffer Invalidation control for the speculation buffer and the single entry buffer 31 2 Modes of operation The FMC only operates when a bus master accesses the flash memory For...

Page 583: ...ge is accessed The cache is a 4 way set associative cache with 2 sets The ways are numbered 0 3 and the sets are numbered 0 1 The following table elaborates on the tag valid and data entries Table 31...

Page 584: ...0000_0000h 31 4 10 596 4001_F20C Cache Data Storage lowermost word FMC_DATAW0S0LM 32 R W 0000_0000h 31 4 11 596 4001_F210 Cache Data Storage uppermost word FMC_DATAW0S1UM 32 R W 0000_0000h 31 4 8 595...

Page 585: ...600 4001_F25C Cache Data Storage lowermost word FMC_DATAW2S1LM 32 R W 0000_0000h 31 4 19 600 4001_F260 Cache Data Storage uppermost word FMC_DATAW3S0UM 32 R W 0000_0000h 31 4 20 601 4001_F264 Cache D...

Page 586: ...occur 19 Reserved This field is reserved 18 M2PFD Master 2 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master This...

Page 587: ...by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 3 2 M1AP 1 0 Master 1 Access Protection This field controls whethe...

Page 588: ...s time of the flash array expressed in system clock cycles and RWSC is defined as Access time of flash array system clocks RWSC 1 The FMC automatically calculates this value based on the ratio of the...

Page 589: ...uffer and single entry buffer are immediately cleared This bit always reads as zero 0 Speculation buffer and single entry buffer are not affected 1 Invalidate clear speculation buffer and single entry...

Page 590: ...s whether the single entry page buffer is enabled in response to flash read accesses A high to low transition of this enable forces the page buffer to be invalidated 0 Single entry buffer is disabled...

Page 591: ...0 1 In TAGVDWxSy x denotes the way and y denotes the set This section represents tag vld information for all sets n 0 1 in way 0 Address 4001_F000h base 100h offset 4d i where i 0d to 1d Bit 31 30 29...

Page 592: ...R 0 cache_tag W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R cache_tag 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW1Sn field descriptions Field Desc...

Page 593: ...R 0 cache_tag W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R cache_tag 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW2Sn field descriptions Field Descr...

Page 594: ...R 0 cache_tag W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R cache_tag 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW3Sn field descriptions Field Desc...

Page 595: ...tion data 127 96 Bits 127 96 of data entry 31 4 9 Cache Data Storage mid upper word FMC_DATAW0SnMU The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are number...

Page 596: ...ription data 63 32 Bits 63 32 of data entry 31 4 11 Cache Data Storage lowermost word FMC_DATAW0SnLM The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are numb...

Page 597: ...tion data 127 96 Bits 127 96 of data entry 31 4 13 Cache Data Storage mid upper word FMC_DATAW1SnMU The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are numbe...

Page 598: ...ription data 63 32 Bits 63 32 of data entry 31 4 15 Cache Data Storage lowermost word FMC_DATAW1SnLM The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are numb...

Page 599: ...tion data 127 96 Bits 127 96 of data entry 31 4 17 Cache Data Storage mid upper word FMC_DATAW2SnMU The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are numbe...

Page 600: ...ription data 63 32 Bits 63 32 of data entry 31 4 19 Cache Data Storage lowermost word FMC_DATAW2SnLM The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are numb...

Page 601: ...tion data 127 96 Bits 127 96 of data entry 31 4 21 Cache Data Storage mid upper word FMC_DATAW3SnMU The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are numbe...

Page 602: ...iption data 63 32 Bits 63 32 of data entry 31 4 23 Cache Data Storage lowermost word FMC_DATAW3SnLM The cache of sixteen 128 bit entries is a 4 way set associative cache with 2 sets The ways are numbe...

Page 603: ...lacement The single entry buffer is enabled 31 5 2 Configuration options Though the default configuration provides a high degree of flash acceleration advanced users may desire to customize the FMC bu...

Page 604: ...de and or data For example consider the following scenario Assume a system with a 4 1 core to flash clock ratio and with speculative reads enabled The core requests eight sequential longwords in back...

Page 605: ...ecause the Flash Memory module manages them directly As a result if an application is executing flash memory commands the FMC s cache might need to be disabled and or flushed to prevent the possibilit...

Page 606: ...Initialization and application information KV4x Reference Manual Rev 2 02 2015 606 Preliminary Freescale Semiconductor Inc...

Page 607: ...y the erase operation restores bits from 0 to 1 bits cannot be programmed from a 0 to a 1 CAUTION A flash memory location must be in the erased state before being programmed Cumulative programming of...

Page 608: ...orized access to selected code segments Automated built in program and erase algorithms with verify 32 1 1 2 Other Flash Memory Module Features Internal high voltage supply generator for flash memory...

Page 609: ...ry controller in the flash memory module Flash block A macro within the flash memory module which provides the nonvolatile memory storage Flash Memory Module All flash blocks plus a flash management u...

Page 610: ...d from the last erase operation not from the programming time RWW Read While Write The ability to simultaneously read from one memory resource while commanded operations are active in another memory r...

Page 611: ...1 Flash security byte Refer to the description of the Flash Security Register FSEC 32 3 2 Program Flash IFR Map The program flash IFR is nonvolatile information memory that can be read freely but the...

Page 612: ...e Field can be read any number of times This section of the program flash IFR is accessed in 4 byte or 8 Byte records using the Read Once and Program Once commands see Read Once Command and Program On...

Page 613: ...Registers FTFA_FCCOB5 8 R W 00h 32 3 3 5 619 4002_000B Flash Common Command Object Registers FTFA_FCCOB4 8 R W 00h 32 3 3 5 619 4002_000C Flash Common Command Object Registers FTFA_FCCOBB 8 R W 00h 3...

Page 614: ...only Access Registers FTFA_SACCH0 8 R Undefined 32 3 3 8 623 4002_0024 Supervisor only Access Registers FTFA_SACCL3 8 R Undefined 32 3 3 8 623 4002_0025 Supervisor only Access Registers FTFA_SACCL2 8...

Page 615: ...s cleared by writing a 1 to it Writing a 0 to RDCOLERR has no effect 0 No collision error detected 1 Collision error detected 5 ACCERR Flash Access Error Flag Indicates an illegal access has occurred...

Page 616: ...CCIE Command Complete Interrupt Enable Controls interrupt generation when a flash command completes 0 Command complete interrupt disabled 1 Command complete interrupt enabled An interrupt request is...

Page 617: ...field is reserved and always has the value 0 0 Reserved This field is reserved This read only field is reserved and always has the value 0 32 3 3 3 Flash Security Register FTFA_FSEC This read only reg...

Page 618: ...state of the FSLACC bits is only relevant when SEC is set to secure When SEC is set to unsecure the FSLACC setting does not matter 00 Freescale factory access granted 01 Freescale factory access deni...

Page 619: ...OB1 FCCOBB Address 4002_0000h base 4h offset 1d i where i 0d to 11d Bit 7 6 5 4 3 2 1 0 Read CCOBn Write Reset 0 0 0 0 0 0 0 0 FTFA_FCCOBn field descriptions Field Description CCOBn The FCCOB register...

Page 620: ...ses a big endian addressing convention For all command parameter fields larger than 1 byte the most significant data resides in the lowest FCCOB register number The FCCOB register group may be read an...

Page 621: ...program flash protection byte Address 4002_0000h base 10h offset 1d i where i 0d to 3d Bit 7 6 5 4 3 2 1 0 Read PROT Write Reset x x x x x x x x Notes x Undefined at reset FTFA_FPROTn field descriptio...

Page 622: ...ACC registers define which program flash segments are restricted to data read or execute only or both data and instruction fetches The eight XACC registers allow up to 64 restricted segments of equal...

Page 623: ...sh segments are restricted to supervisor only or user and supervisor access The eight SACC registers allow up to 64 restricted segments of equal memory size Supervisor only access register Program fla...

Page 624: ...n SA Supervisor only access control 0 Associated segment is accessible in supervisor mode only 1 Associated segment is accessible in user or supervisor mode 32 3 3 9 Flash Access Segment Size Register...

Page 625: ...ssions All bits in the register are read only The contents of this register are loaded during the reset sequence Address 4002_0000h base 2Bh offset 4002_002Bh Bit 7 6 5 4 3 2 1 0 Read NUMSG Write Rese...

Page 626: ...lash size 32 Program flash size 32 Program flash size 32 Program flash size 32 Program flash size 32 Program flash size 32 Program flash size 32 FPROT3 PROT0 0x0_0000 FPROT3 PROT1 FPROT3 PROT2 FPROT3...

Page 627: ...gram flash Last program flash address Program flash size 64 XACCL3 XA1 Program flash size 64 XACCL3 XA2 Program flash size 64 XACCL3 XA3 Program flash size 64 XACCL3 XA4 Program flash size 64 XACCL0 X...

Page 628: ...dule can generate interrupt requests to the MCU upon the occurrence of various flash events These interrupt events and their associated status and control bits are shown in the following table Table 3...

Page 629: ...s VLPR VLPW VLPS the flash memory module does not accept flash commands 32 4 5 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read The...

Page 630: ...mmands available 32 4 8 1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 32 47 The flash memory module performs various checks on the command...

Page 631: ...ch are unique to each command If the parameter check fails the FSTAT ACCERR access error flag is set FSTAT ACCERR reports invalid instruction codes and out of bounds addresses Usually access errors su...

Page 632: ...Parameters Availability Check Results from previous command Read FSTAT register Write 0x30 to FSTAT register no yes no yes Previous command complete no CCIF 1 yes START Figure 32 47 Generic flash com...

Page 633: ...ose stored in the program flash 32 4 9 Margin Read Commands The Read 1s commands Read 1s All Blocks and Read 1s Section and the Program Check command have a margin choice parameter that allows the use...

Page 634: ...completion of an erase or program command early in the cycling life Factory margin levels can be used to check that flash memory contents have adequate margin for long term data retention at the norm...

Page 635: ...first double phrase to be verified 3 Flash address 7 0 1 of the first double phrase to be verified 4 Number of double phrases to be verified 15 8 5 Number of double phrases to be verified 7 0 6 Read...

Page 636: ...ress 15 8 3 Flash address 7 0 1 4 Margin Choice 8 Byte 0 expected data 9 Byte 1 expected data A Byte 2 expected data B Byte 3 expected data 1 Must be longword aligned Flash address 1 0 00 Upon clearin...

Page 637: ...controlled segment and the Erase All Blocks or the Read 1s All Blocks command has not successfully completed since the last reset FSTAT FPVIOL Either of the margin reads does not match the expected d...

Page 638: ...if an invalid resource code is provided or if the address for the applicable area is out of range Table 32 53 Read Resource Command Error Handling Error Condition Error Bit Command not available in cu...

Page 639: ...The CCIF flag is set after the Program Longword operation completes The supplied address must be longword aligned flash address 1 0 00 Byte 3 data is written to the supplied byte address start Byte 2...

Page 640: ...s is supplied FSTAT ACCERR Flash address is not double phrase aligned FSTAT ACCERR The selected program flash sector is protected FSTAT FPVIOL The selected program flash sector is located in an XA con...

Page 641: ...he request to resume the Erase Flash Sector operation CCIF is cleared and the request to suspend the operation again ERSSUSP is set This minimum time period is required to ensure that the Erase Flash...

Page 642: ...SUSP Execute Yes DONE No ERSSUSP 1 Save Erase Algo Set CCIF No Yes Start New Resume Erase No Abort User Cmd Interrupt Suspend Set SUSPACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Co...

Page 643: ...setting the FSEC SEC field to the unsecure state The security byte in the flash configuration field see Flash Configuration Field Description remains unaffected by the Read 1s All Blocks command If th...

Page 644: ...byte 3 value 8 Program Once byte 4 value index 0x10 0x13 9 Program Once byte 5 value index 0x10 0x13 10 Program Once byte 6 value index 0x10 0x13 11 Program Once byte 7 value index 0x10 0x13 After cle...

Page 645: ...ce byte 6 value index 0x10 0x13 11 Program Once byte 7 value index 0x10 0x13 After clearing CCIF to launch the Program Once command the flash memory module first verifies that the selected record is e...

Page 646: ...ation field see Flash Configuration Field Description are erased by the Erase All Blocks command If the erase verify fails the FSTAT MGSTAT0 bit is set The CCIF flag is set after the Erase All Blocks...

Page 647: ...SAREQ bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command 32 4 10 10 Verify Backdoor Access Key Command The Verify Ba...

Page 648: ...y Backdoor Access Key command fails with an access error The CCIF flag is set after the Verify Backdoor Access Key operation completes Table 32 68 Verify Backdoor Access Key Command Error Handling Err...

Page 649: ...knowledge of the contents of the 8 byte backdoor key value stored in the Flash Configuration Field see Flash Configuration Field Description If the FSEC KEYEN bits are in the enabled state the Verify...

Page 650: ...has no effect on the program and erase protections defined in the program flash protection registers If the backdoor keys successfully match the unsecured chip has full control of the contents of the...

Page 651: ...bit or 32 bit programmable shift register Programmable initial seed value and polynomial Option to transpose input data or output data the CRC result bitwise or bytewise This option is required for c...

Page 652: ...y CRC calculation in progress stops when the MCU enters a low power mode that disables the module clock It resumes after the clock is enabled or via the system reset for exiting the low power mode Clo...

Page 653: ...2 1 0 R HU HL LU LL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_DATA field descriptions Field Description 31 24 HU CRC High Upper Byte In 16 bit CRC mode CTRL TCRC is 0...

Page 654: ...nal Half word Writable and readable in 32 bit CRC mode CTRL TCRC is 1 This field is not writable in 16 bit CRC mode CTRL TCRC is 0 LOW Low Polynominal Half word Writable and readable in both 32 bit an...

Page 655: ...transposed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 FXOR Complement Read Of CRC Data Register Some CRC protocols require the final checksum to...

Page 656: ...o compute a 16 bit CRC 1 Clear CRC_CTRL TCRC to enable 16 bit CRC mode 2 Program the transpose and complement options in the CTRL register as required for the CRC calculation See Transpose feature and...

Page 657: ...C result complement for details 33 3 3 Transpose feature By default the transpose feature is not enabled However some CRC standards require the input data and or the final checksum to be transposed Th...

Page 658: ...Transpose type 01 3 CTRL TOT or CTRL TOTR is 10 Both bits in bytes and bytes are transposed reg 31 0 becomes reg 0 7 reg 8 15 reg 16 23 reg 24 31 31 31 0 0 Figure 33 6 Transpose type 10 4 CTRL TOT or...

Page 659: ...ransposition resides in the CRC HU HL fields The user software must account for this situation when reading the 16 bit CRC result so reading 32 bits is preferred 33 3 4 CRC result complement When CTRL...

Page 660: ...Functional description KV4x Reference Manual Rev 2 02 2015 660 Preliminary Freescale Semiconductor Inc...

Page 661: ...ARA_OUT12 and PDB0 channel trigger outputs can trigger ADCA and ADCB parallel sampling conversion via SYNC0 input XBARA_OUT13 and PDB1 channel trigger outputs can trigger ADCB conversions via SYNC1 in...

Page 662: ...power mode 34 1 5 ADC channel muxing Each of ADCA_ANA6 7 and ADCB_ANB6 7 have analog 8 to 1 muxing to expand the channels The muxing is controlled by SIM_ADCOPT Introduction 34 2 1 Overview The analo...

Page 663: ...nverters operating asynchronously to each other in parallel A scan can pause and await new SYNC input prior to continuing Gains the input signal by x1 x2 or x4 Optional interrupts at end of scan if an...

Page 664: ...al Descriptions 34 3 1 Overview Table 34 2 External Signal Properties Name I O Type Function Reset State Notes ANA0 ANB7 I Analog Input Pins n a VREFH I Voltage Reference Pin of ADCA n a Selectable be...

Page 665: ...ices and signal routing 2 04pf 3 Equivalent resistance for the ESD isolation resistor and the channel select multiplexer 500 4 Sampling capacitor at the sample and hold circuit 1pf Figure 34 2 Equival...

Page 666: ...ster ADC_ZXCTRL1 16 R W 0000h 34 4 3 676 4005_C006 ADC Zero Crossing Control 2 Register ADC_ZXCTRL2 16 R W 0000h 34 4 4 677 4005_C008 ADC Channel List Register 1 ADC_CLIST1 16 R W 3210h 34 4 5 679 400...

Page 667: ...00h 34 4 15 691 4005_C02E ADC Result Registers with sign extension ADC_RSLT9 16 R W 0000h 34 4 15 691 4005_C030 ADC Result Registers with sign extension ADC_RSLT10 16 R W 0000h 34 4 15 691 4005_C032 A...

Page 668: ...4 16 692 4005_C05A ADC Low Limit Registers ADC_LOLIM15 16 R W 0000h 34 4 16 692 4005_C05C ADC High Limit Registers ADC_HILIM0 16 R W 7FF8h 34 4 17 693 4005_C05E ADC High Limit Registers ADC_HILIM1 16...

Page 669: ...4 18 693 4005_C086 ADC Offset Registers ADC_OFFST5 16 R W 0000h 34 4 18 693 4005_C088 ADC Offset Registers ADC_OFFST6 16 R W 0000h 34 4 18 693 4005_C08A ADC Offset Registers ADC_OFFST7 16 R W 0000h 34...

Page 670: ...cans except parallel scans in the B converter when CTRL2 SIMULT 0 Non simultaneous parallel scan modes allow independent parallel scanning in the A and B converter Bits 14 13 12 and 11 in CTRL2 are us...

Page 671: ...e to the SCTRL SCn bits CTRL1 SYNC0 is cleared in ONCE mode CTRL1 SMODE 000 or 001 when the first SYNC input is detected This prevents unintentionally starting a new scan after the first scan has comp...

Page 672: ...ANA2 ANA3 Both configured as single ended inputs x1xx Inputs ANB0 ANB1 Configured as differential pair ANB0 is and ANB1 is x0xx Inputs ANB0 ANB1 Both configured as single ended inputs 1xxx Inputs ANB...

Page 673: ...he process repeats perpetually until the CTRL1 STOP0 bit is set While a loop mode is running any additional start commands or sync pulses are ignored unless the scan is paused using the SCTRL SC bits...

Page 674: ...ses see CTRL2 SYNC1 bit or writes to the CTRL2 START1 bit are ignored until this bit has been cleared After the ADC is in stop mode the results registers can be modified by the processor Any changes t...

Page 675: ...ts return the max value 2 12 1 when the input is VREFH and the input is VREFLO return 0 when the input is at VREFLO and the input is at VREFH and scale linearly between based on the voltage difference...

Page 676: ...d the maximum frequency This clock is used by ADCA during all scans and is used by ADCB during sequential scan modes and during parallel simultaneous scan modes 34 4 3 ADC Zero Crossing Control 1 Regi...

Page 677: ...o Crossing enabled for any sign change 3 2 ZCE1 Zero crossing enable 1 00 Zero Crossing disabled 01 Zero Crossing enabled for positive to negative sign change 10 Zero Crossing enabled for negative to...

Page 678: ...change 11 Zero Crossing enabled for any sign change 7 6 ZCE11 Zero crossing enable 11 00 Zero Crossing disabled 01 Zero Crossing enabled for positive to negative sign change 10 Zero Crossing enabled...

Page 679: ...NB4 ANB5 1101 Single Ended ANB5 Differential ANB4 ANB5 1110 Single Ended ANB6 Differential ANB6 ANB7 1111 Single Ended ANB7 Differential ANB6 ANB7 11 8 SAMPLE2 Sample Field 2 0000 Single Ended ANA0 Di...

Page 680: ...Single Ended ANA0 Differential ANA0 ANA1 0001 Single Ended ANA1 Differential ANA0 ANA1 0010 Single Ended ANA2 Differential ANA2 ANA3 0011 Single Ended ANA3 Differential ANA2 ANA3 0100 Single Ended ANA...

Page 681: ...A2 ANA3 0100 Single Ended ANA4 Differential ANA4 ANA5 0101 Single Ended ANA5 Differential ANA4 ANA5 0110 Single Ended ANA6 Differential ANA6 ANA7 0111 Single Ended ANA7 Differential ANA6 ANA7 1000 Sin...

Page 682: ...ntial ANB2 ANB3 1011 Single Ended ANB3 Differential ANB2 ANB3 1100 Single Ended ANB4 Differential ANB4 ANB5 1101 Single Ended ANB5 Differential ANB4 ANB5 1110 Single Ended ANB6 Differential ANB6 ANB7...

Page 683: ...ANB2 ANB3 1100 Single Ended ANB4 Differential ANB4 ANB5 1101 Single Ended ANB5 Differential ANB4 ANB5 1110 Single Ended ANB6 Differential ANB6 ANB7 1111 Single Ended ANB7 Differential ANB6 ANB7 7 4 S...

Page 684: ...0 9 8 7 6 5 4 3 2 1 0 Read SAMPLE15 SAMPLE14 SAMPLE13 SAMPLE12 Write Reset 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 ADC_CLIST4 field descriptions Field Description 15 12 SAMPLE15 Sample Field 15 0000 Single En...

Page 685: ...gle Ended ANA3 Differential ANA2 ANA3 0100 Single Ended ANA4 Differential ANA4 ANA5 0101 Single Ended ANA5 Differential ANA4 ANA5 0110 Single Ended ANA6 Differential ANA6 ANA7 0111 Single Ended ANA7 D...

Page 686: ...d subsequent ADC acquisition also does not occur Remembering that the ADC sequentially scans in order SAMPLE0 SAMPLE1 SAMPLE2 etc thus if ADC_SDIS 0xFFF7 then an ADC scan acquires SAMPLE0 while SAMPLE...

Page 687: ...cates whether a scan is in progress This refers to any scan except a B converter scan in non simultaneous parallel scan modes 0 Idle state 1 A scan cycle is in progress The ADC will ignore all sync pu...

Page 688: ...f 0000h is programmed into the offset register the result will always be greater than or equal to zero and no zero crossing can occur because the sign of the result will not change This interrupt asse...

Page 689: ...been read 1 Sample ready to be read 34 4 12 ADC Low Limit Status Register ADC_LOLIMSTAT The low limit status register latches in the result of the comparison between the result of the sample and the r...

Page 690: ...ue of one to that specific bit Address 4005_C000h base 18h offset 4005_C018h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read HLS 15 0 Write w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_HILIMSTAT field...

Page 691: ...n Address 4005_C000h base 1Ch offset 2d i where i 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SEXT RSLT 0 Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_RSLTn field descriptions Field De...

Page 692: ...er is used for the comparison of Result High Limit The low limit register is used for the comparison of Result Low Limit The limit checking can be disabled by programming the respective limit register...

Page 693: ...Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 ADC_HILIMn field descriptions Field Description 15 Reserved This field is reserved This read only field is reserved and always has the value 0 14 3 HLMT High Limi...

Page 694: ...generator have a manual power control bit capable of putting that component into the power down state Converters have other mechanisms that can automatically put them into the power down state Idle st...

Page 695: ...bit is asserted immediately following a write of 1 to PWR PD1 It is de asserted PWR PUDELAY ADC clock cycles after a write of 0 to PWR PD1 if PWR APD is 0 This bit can be read as a status bit to dete...

Page 696: ...s bit powers down converter B immediately The results of a scan using converter B will be invalid while PWR PD1 is asserted When PWR PD1 is cleared converter B is either continuously powered up PWR AP...

Page 697: ...REFLO reference for all conversions in converter 1 0 VREFL pad 1 ANB3 13 SEL_VREFH_A Select V REFH Source This bit selects the source of the VREFH reference for all conversions in converter 0 0 VREFH...

Page 698: ...criptions Field Description 15 14 GAIN7 Gain Control Bit 7 GAIN 7 controls ANA7 00 x1 amplification 01 x2 amplification 10 x4 amplification 11 reserved 13 12 GAIN6 Gain Control Bit 6 GAIN 6 controls A...

Page 699: ...ANA0 00 x1 amplification 01 x2 amplification 10 x4 amplification 11 reserved 34 4 22 Gain Control 2 Register ADC_GC2 The gain control registers are used to control amplification of each of the 16 inpu...

Page 700: ...10 x4 amplification 11 reserved 9 8 GAIN12 Gain Control Bit 12 GAIN 12 controls ANB4 00 x1 amplification 01 x2 amplification 10 x4 amplification 11 reserved 7 6 GAIN11 Gain Control Bit 11 GAIN 11 cont...

Page 701: ...order from SC0 to SC15 During simultaneous parallel scan modes the bits are used in order from SC0 to SC3 and SC8 to SC11 In non simultaneous parallel scans ADCA uses the bits in order from SC0 to SC3...

Page 702: ...trol Bits These bits configure the clock speed at which the ADCB can operate Faster conversion speeds require greater current consumption 00 Conversion clock frequency 6 25 MHz current consumption per...

Page 703: ...controlled by CTRL3 SCNT0 The default value is 0 which corresponds to a sampling time of 2 ADC clocks Each increment of CTRL3 SCNT1 corresponds to an additional ADC clock cycle of sampling time with a...

Page 704: ...nverters store their results in an accessible buffer awaiting further processing The conversion process is initiated either by a SYNC signal or by writing a 1 to a START bit Starting a single conversi...

Page 705: ...3 ANB4 ANB5 ANB6 ANB7 Figure 34 94 ADC Sequential Scan Mode In parallel scan mode eight of the sixteen samples are allocated to converter A and eight are allocated to converter B Two converters operat...

Page 706: ...ANA 4 5 ANA 6 7 ANB 0 1 ANB 2 3 ANB 4 5 ANB 6 7 When they are so configured a reference to either member of the differential pair by a sample slot results in a differential measurement using that dif...

Page 707: ...occur any time after the SYNC pulse including while the scan is still in process Optional interrupts can be generated at the end of a scan sequence Interrupts are available simply to indicate that a s...

Page 708: ...ction Converter A To Interface Function Converter B ADCB VREFH ADCB VREFL Figure 34 96 Input Select Multiplex The multiplexing for conversions in different operating modes is as follows Sequential sin...

Page 709: ...e ended The two 1 of 8 select multiplexes can be set for the appropriate input line The lower switch is closed providing VREFH VREFL 2 to the differential input of the A D The upper switch is always c...

Page 710: ...240 ns not including sample or post processing time ANA0 ANA7 ANB0 ANB1 Analog Input Select Multiplex Analog Input Select Multiplex Interface Function Program Gain Interface Function Program Gain Mul...

Page 711: ...ended ANB 4 5 differential ANB 6 7 single ended 34 5 2 1 1 Single Ended Samples The ADC module performs a ratio metric conversion For single ended measurements the digital result is proportional to th...

Page 712: ...value from each sample and the resultant value is stored in the result register RSLT The raw ADC value and the RSLT values are checked for limit violations and zero crossing as shown Appropriate inter...

Page 713: ...and ANB6 7 can be set to be measured differentially using the CHNCFG field If a sample refers to an input that is not configured as a member of a differential pair a single ended measurement is made I...

Page 714: ...Setting the CTRL1 STOP0 bit stops and prevents the initiation of scanning in both converters Setting CTRL2 SIMULT 0 non simultaneous mode causes parallel scanning to operate independently in the A and...

Page 715: ...power modes are discussed in order from from highest to lowest power usage Mode Description Normal power At least one ADC converter is powered up PWR PD0 or PD1 is 0 the PWR APD and ASB bits are both...

Page 716: ...rsion clock and revert power up the converters and stabilize them in the standby current mode This is the slowest and lowest power operational configuration of the ADC Powerdown Both ADC converters an...

Page 717: ...an during the PWR PUDELAY are ignored until the appropriate PWR PSTSn bits are cleared Any attempt to use a converter when it is powered down or with the voltage references disabled will result in inv...

Page 718: ...k is sourced by fast bus clock in normal mode and MCGIRC in stop mode and CTRL2 DIV0 and PWR2 DIV1 should be configured so that conversion clock frequency falls between 100 kHz and 25 MHz Operating th...

Page 719: ...ck to the conversion clock at the start of a scan than auto powerdown mode which uses only the conversion clock as the ADC clock source but fully powers down the converters when idle The standby curre...

Page 720: ...w limit exceeded error occurs when the current result value is less than the low limit register value The raw result value is compared to LOLIM LLMT before the offset register value is subtracted High...

Page 721: ...nterrupt EOSIx Zero crossing or limit error interrupt ZCI LLMTI and HLMTI sample0 sample1 Ignored CLK ADC CLK Sync Pulse or Start Bit Multiplex Select CIP ADCSTAT Bit 15 Sample Hold ADC Result Latched...

Page 722: ...The figure shown here illustrates the case in which PWR APD and ASB are not in use When the PWR APD or ASB bit is set the sync pulse or start powers up the ADC waits for a number of ADC clocks determi...

Page 723: ...N3 pin PTC9 pin81 of 100 IN4 input channel input CMP0_IN4 pin pin28 of 100 IN5 input channel input CMP0_IN5 pin PTE29 pin26 of 100 IN6 input channel input bandgap IN7 input channel input 6bDAC WindowI...

Page 724: ...in43 of 100 IN2 input channel input CMP2_IN2 pin PTB2 pin55 of 100 IN3 input channel input CMP2_IN3 pin pin28 of 100 IN4 input channel input CMP2_IN4 pin PTC6 pin78 of 100 IN5 input channel input CMP2...

Page 725: ...e of the supply voltage known as rail to rail operation The Analog MUX ANMUX provides a circuit for selecting an analog input signal from eight channels One signal is provided by the 6 bit digital to...

Page 726: ...al SAMPLE signal or scaled bus clock External hysteresis can be used at the same time that the output filter is used for internal functions Two software selectable performance levels Shorter propagati...

Page 727: ...e ANMUX has the following features Two 8 to 1 channel mux Operational over the entire supply range 35 2 4 CMP DAC and ANMUX diagram The following figure shows the block diagram for the High Speed Comp...

Page 728: ...Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INM Sample input Figure 35 1 CMP DAC and ANMUX block diagram 35 2 5 CMP block diagram T...

Page 729: ...E 1 the comparator output will be sampled on every bus clock when WINDOW 1 to generate COUTA Sampling does NOT occur when WINDOW 0 The Filter block is bypassed when not in use The Filter block acts as...

Page 730: ...ster CMP1_FPR 8 R W 00h 35 3 3 733 4007_300B CMP Status and Control Register CMP1_SCR 8 R W 00h 35 3 4 733 4007_300C DAC Control Register CMP1_DACCR 8 R W 00h 35 3 5 734 4007_300D MUX Control Register...

Page 731: ...0 2 consecutive samples must agree 011 3 consecutive samples must agree 100 4 consecutive samples must agree 101 5 consecutive samples must agree 110 6 consecutive samples must agree 111 7 consecutive...

Page 732: ...imer resource 0 Trigger mode is disabled 1 Trigger mode is enabled 4 PMODE Power Mode Select See the electrical specifications table in the device Data Sheet for details 0 Low Speed LS Comparison mode...

Page 733: ...set 0 0 0 0 0 0 0 0 CMPx_FPR field descriptions Field Description FILT_PER Filter Sample Period Specifies the sampling period in bus clock cycles of the comparator output filter when CR1 SE 0 Setting...

Page 734: ...ects a rising edge on COUT when set during normal operation CFR is cleared by writing 1 to it During Stop modes CFR is edge sensitive 0 Rising edge on COUT has not been detected 1 Rising edge on COUT...

Page 735: ...1 0 Read Reserved 0 PSEL MSEL Write Reset 0 0 0 0 0 0 0 0 CMPx_MUXCR field descriptions Field Description 7 Reserved Bit can be programmed to zero only This field is reserved 6 Reserved This field is...

Page 736: ...INM CMPO is high when the non inverting input is greater than the inverting input and is low when the non inverting input is less than the inverting input This signal can be selectively inverted by s...

Page 737: ...ual modes are discussed below Table 35 37 Comparator sample filter controls Mode CR1 EN CR1 WE CR1 SE CR0 FILTER_C NT FPR FILT_PER Operation 1 0 X X X X Disabled See the Disabled mode 1 2A 1 0 0 0x00...

Page 738: ...drive a fault input for example for a motor control module such as FTM it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the...

Page 739: ...is powered and active CMPO may be optionally inverted but is not subject to external sampling or filtering Both window control and filter blocks are completely bypassed SCR COUT is updated continuous...

Page 740: ...ctive The path from analog inputs to COUTA is combinational unclocked Windowing control is completely bypassed COUTA is sampled whenever a rising edge is detected on the filter block clock input The o...

Page 741: ...nally derived 35 4 1 4 Sampled Filtered mode s 4A 4B In Sampled Filtered mode the analog comparator block is powered and active The path from analog inputs to COUTA is combinational unclocked Windowin...

Page 742: ...AMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt control Clock prescaler To other SOC functions Figure 35 36 Sampled Filter...

Page 743: ...at now CR0 FILTER_CNT 1 which activates filter operation 35 4 1 5 Windowed mode s 5A 5B The following figure illustrates comparator operation in the Windowed mode ignoring latency of the analog compar...

Page 744: ...ck COS 0x01 IER F CFR F WINDOW SAMPLE Polarity select Window control Filter block Interrupt control divided bus clock Clock prescaler CMPO Internal bus To other SOC functions Figure 35 39 Windowed mod...

Page 745: ...on Depending upon the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully considered fo...

Page 746: ...tched value is held when WINDOW 0 IRQ EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 0 1 WE 1 0 SE 0 CGMUX COS FILT_PER 0 1 FILT_PER bus clock COS IER F CFR F WINDOW SAM...

Page 747: ...Startup and operation A typical startup sequence is listed here The time required to stabilize COUT will be the power on delay of the comparators plus the largest propagation delay from a selected an...

Page 748: ...nput voltages differ by less than the offset voltage of the differential comparator 35 4 4 1 Enabling filter modes Filter modes can be enabled by Setting CR0 FILTER_CNT 0x01 and Setting FPR FILT_PER t...

Page 749: ...actual output change within the nominal latency is the probability of a correct sample raised to the power of CR0 FILTER_CNT The following table summarizes maximum latency values for the various modes...

Page 750: ...DMA support is enabled by setting SCR DMAEN and the interrupt is enabled by setting SCR IER SCR IEF or both the corresponding change on COUT forces a DMA transfer request rather than a CPU interrupt i...

Page 751: ...tains a 64 tap resistor ladder network and a 64 to 1 multiplexer which selects an output voltage from one of 64 distinct levels that outputs from DACO It is controlled through the DAC Control Register...

Page 752: ...as no interrupts 35 13 CMP Trigger Mode CMP and DAC are configured to CMP Trigger mode when CMP_CR1 TRIGM is set to 1 In addition the CMP must be enabled If the DAC is to be used as a reference to the...

Page 753: ...B0_DAC_trig and PDB1_DAC_trig outputs 36 1 2 12 bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC 36 1 3 12 bit DAC Refe...

Page 754: ...mable reference generator output The voltage output range is from 1 4096 Vin to Vin and the step is 1 4096 Vin where Vin is the input voltage Vin can be selected from two reference sources Static oper...

Page 755: ...BBIEN OR dac_interrupt DACTRGSE LPEN DACRFS DACREF_1 Vin Vo Data Buffer Figure 36 1 DAC block diagram 36 5 Memory map register definition The DAC has registers to control analog comparator and program...

Page 756: ...AC_DAT8L 8 R W 00h 36 5 1 757 4003_F011 DAC Data High Register DAC_DAT8H 8 R W 00h 36 5 2 757 4003_F012 DAC Data Low Register DAC_DAT9L 8 R W 00h 36 5 1 757 4003_F013 DAC Data High Register DAC_DAT9H...

Page 757: ...igh Register DAC_DATnH Address 4003_F000h base 1h offset 2d i where i 0d to 15d Bit 7 6 5 4 3 2 1 0 Read 0 DATA1 Write Reset 0 0 0 0 0 0 0 0 DAC_DATnH field descriptions Field Description 7 4 Reserved...

Page 758: ...ermark level 1 The DAC buffer read pointer has reached the watermark level 1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag In FIFO mode it is FIFO nearly empty flag It is set when only one data...

Page 759: ...ware trigger is selected and buffer is enabled writing 1 to this field will advance the buffer read pointer once 0 The DAC soft trigger is not valid 1 The DAC soft trigger is valid 3 LPEN DAC Low Powe...

Page 760: ...per limit DACBUP SR DACBFWMF will be set This allows user configuration of the watermark interrupt In FIFO mode it is FIFO watermark select field 00 In normal mode 1 word In FIFO mode 2 or less than 2...

Page 761: ...writable and user can configure it to the same address to reset FIFO as empty 36 6 Functional description The 12 bit DAC module can select one of the two reference inputs DACREF_1 and DACREF_2 as the...

Page 762: ...he buffer works as a circular buffer The read pointer increases by one every time the trigger occurs When the read pointer reaches the upper limit it goes to 0 directly in the next trigger event Buffe...

Page 763: ...ACDATx will return the DATA addressed by the access address to the data buffer and both write pointer and read pointer in FIFO mode will NOT be changed by read access FIFO write can be happened when D...

Page 764: ...ode In low power stop modes the DAC is fully shut down NOTE The assignment of module modes to core modes is chip specific For module to core mode assignments see the chapter that describes how modules...

Page 765: ...cted to PWMA0_EXTA XBARA_OUT20 PWMA1_EXTA XBARA_OUT21 PWMA2_EXTA XBARA_OUT22 PWMA3_EXTA XBARA_OUT23 PWMA0_EXT_SYNC XBARA_OUT24 PWMA1_EXT_SYNC XBARA_OUT25 PWMA2_EXT_SYNC XBARA_OUT26 PWMA3_EXT_SYNC XBAR...

Page 766: ...r double buffered VALx registers Submodule 0 PWMA_WR0 output is connected to DMAMUX0 ch 6 Submodule 1 PWMA_WR1 output is connected to DMAMUX0 ch 7 Submodule 2 PWMA_WR2 output is connected to DMAMUX0 c...

Page 767: ...ndependently programmable PWM output polarity Independent top and bottom deadtime insertion Each complementary pair can operate with its own PWM frequency and deadtime values Individual software contr...

Page 768: ...eactivated assuming they were active beforehand when these modes are exited Table 37 1 Modes when PWM Operation is Restricted Mode Description Stop PWM outputs are inactive Wait PWM outputs are driven...

Page 769: ...MB2 PWMX2 EXT_FORCE Interrupts Sub Module 0 Sub Module 3 PWMA3 PWMB3 PWMX3 Master Sync Master Force FAULT0 3 Faults Master Reload Fault Channel 0 Figure 37 1 PWM Block Diagram Chapter 37 Pulse Width M...

Page 770: ...Counter preload mux Pin Mux PWM_X Master Sync Master Reload register reloads PWM23 PWM45 Mux Select Logic Aux Clock sub module0 only External Sync Register reload mux Figure 37 2 PWM Submodule Block...

Page 771: ...to force an update of the PWM outputs In this manner the PWM can be synchronized to external circuitry 37 3 6 PWM n _EXTA and PWM n _EXTB Alternate PWM Control Signals These pins allow an alternate s...

Page 772: ...hole This 60 offset is based on the number of registers in a submodule The base address of submodule 2 is equal to the base address of submodule 1 plus this same 60 offset The pattern repeats for the...

Page 773: ...17 793 4003_3024 Status Register PWMA_SM0STS 16 w1c 0000h 37 4 18 794 4003_3026 Interrupt Enable Register PWMA_SM0INTEN 16 R W 0000h 37 4 19 796 4003_3028 DMA Enable Register PWMA_SM0DMAEN 16 R W 0000...

Page 774: ...lue 5 Register PWMA_SM0CVAL5 16 R 0000h 37 4 41 813 4003_3056 Capture Value 5 Cycle Register PWMA_SM0CVAL5CYC 16 R 0000h 37 4 42 813 4003_3060 Counter Register PWMA_SM1CNT 16 R 0000h 37 4 1 780 4003_3...

Page 775: ...nt Register 1 PWMA_SM1DTCNT1 16 R W 07FFh 37 4 24 802 4003_3094 Capture Control A Register PWMA_SM1CAPTCTRLA 16 R W 0000h 37 4 25 802 4003_3096 Capture Compare A Register PWMA_SM1CAPTCOMPA 16 R W 0000...

Page 776: ...h 37 4 5 785 4003_30CC Fractional Value Register 1 PWMA_SM2FRACVAL1 16 R W 0000h 37 4 6 786 4003_30CE Value Register 1 PWMA_SM2VAL1 16 R W 0000h 37 4 7 786 4003_30D0 Fractional Value Register 2 PWMA_S...

Page 777: ...29 807 4003_30FE Capture Compare X Register PWMA_SM2CAPTCOMPX 16 R W 0000h 37 4 30 809 4003_3100 Capture Value 0 Register PWMA_SM2CVAL0 16 R 0000h 37 4 31 809 4003_3102 Capture Value 0 Cycle Register...

Page 778: ...l Value Register 4 PWMA_SM3FRACVAL4 16 R W 0000h 37 4 12 789 4003_313A Value Register 4 PWMA_SM3VAL4 16 R W 0000h 37 4 13 790 4003_313C Fractional Value Register 5 PWMA_SM3FRACVAL5 16 R W 0000h 37 4 1...

Page 779: ...37 4 35 811 4003_316A Capture Value 2 Cycle Register PWMA_SM3CVAL2CYC 16 R 0000h 37 4 36 811 4003_316C Capture Value 3 Register PWMA_SM3CVAL3 16 R 0000h 37 4 37 811 4003_316E Capture Value 3 Cycle Re...

Page 780: ...cessible Address 4003_3000h base 0h offset 96d i where i 0d to 3d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read CNT Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_SMnCNT field descriptions Field De...

Page 781: ...CE Reset 0 0 0 0 0 0 0 0 PWMA_SMnCTRL2 field descriptions Field Description 15 DBGEN Debug Enable When set to one the PWM will continue to run while the chip is in debug mode If the device enters debu...

Page 782: ...d when FORCE_INIT is asserted 11 PWM45_INIT PWM45 Initial Value This read write bit determines the initial value for PWM45 and the value to which it is forced when FORCE_INIT is asserted 10 PWMX_INIT...

Page 783: ...de the PWM module causes updates 111 The external sync signal EXT_SYNC from outside the PWM module causes updates 2 RELOAD_SEL Reload Source Select This read write bit determines the source of the REL...

Page 784: ...le is defined by when the submodule counter matches the VAL0 register and does not have to be half way through the PWM cycle 0 Half cycle reloads disabled 1 Half cycle reloads enabled 10 FULL Full Cyc...

Page 785: ...uffered registers of this submodule are loaded and take effect immediately upon MCTRL LDOK being set In this case it is not necessary to set CTRL FULL or CTRL HALF 1 DBLX PWMX Double Switching Enable...

Page 786: ...ts act as a fractional addition to the value in the VAL1 register which controls the PWM period width The PWM period is computed in terms of IPBus clock cycles This fractional portion is accumulated a...

Page 787: ...originated by the Local Sync from sub module 0 is used to control the timer period the VAL1 register can be free for other functions such as PWM generation without the duty cycle limitation 37 4 8 Fra...

Page 788: ...0 Read FRACVAL3 0 Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_SMnFRACVAL3 field descriptions Field Description 15 11 FRACVAL3 Fractional Value 3 These bits act as a fractional addition to the va...

Page 789: ...VAL4 0 Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_SMnFRACVAL4 field descriptions Field Description 15 11 FRACVAL4 Fractional Value 4 These bits act as a fractional addition to the value in the V...

Page 790: ...1 0 Read FRACVAL5 0 Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_SMnFRACVAL5 field descriptions Field Description 15 11 FRACVAL5 Fractional Value 5 These bits act as a fractional addition to the v...

Page 791: ...ster PWMA_SMnFRCTRL Address 4003_3000h base 20h offset 96d i where i 0d to 3d Bit 15 14 13 12 11 10 9 8 Read TEST 0 FRAC_PU Write Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read 0 FRAC45_ EN 0 FRAC23_...

Page 792: ...is used to enable the fractional cycle edge placement of PWM_A using the FRACVAL2 and FRACVAL3 registers When disabled the fractional cycle edge placement of PWM_A is bypassed NOTE The FRAC23_EN bit i...

Page 793: ...always has the value 0 10 POLA PWM_A Output Polarity This bit inverts the PWM_A output polarity 0 PWM_A output not inverted A high level on the PWM_A pin represents the on or active state 1 PWM_A outp...

Page 794: ...deration of output polarity control 01 Output is forced to logic 1 state prior to consideration of output polarity control 10 Output is tristated 11 Output is tristated PWMXFS PWM_X Fault State These...

Page 795: ...reload cycle since last STS RF clearing 11 CFA1 Capture Flag A1 This bit is set when a capture event occurs on the Capture A1 circuit This bit is cleared by writing a one to this bit position if DMAEN...

Page 796: ...Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read CX1IE CX0IE CMPIE Write Reset 0 0 0 0 0 0 0 0 PWMA_SMnINTEN field descriptions Field Description 15 14 Reserved This field is reserved This read only fie...

Page 797: ...t and DMAEN CB0DE 0 Interrupt request disabled for STS CFB0 1 Interrupt request enabled for STS CFB0 7 CX1IE Capture X 1 Interrupt Enable This bit allows the STS CFX1 flag to create an interrupt reque...

Page 798: ...is bit determines if the selected watermarks are AND ed together or OR ed together in order to create the request 0 Selected FIFO watermarks are OR ed together 1 Selected FIFO watermarks are AND ed to...

Page 799: ...A read requests for the Capture X0 FIFO data when STS CFX0 is set Reset clears this bit Do not set both this bit and INTEN CX0IE 37 4 21 Output Trigger Control Register PWMA_SMnTCTRL Address 4003_3000...

Page 800: ...e PWM outputs the output trigger signals will lead the PWM output edges by 2 3 clock cycles depending on the fractional cycle value being used 0 PWM_OUT_TRIGx will not set when the counter value match...

Page 801: ...o complementary channel operation The values written to the DTCNTx registers are in terms of IPBus clock cycles regardless of the setting of CTRL PRSC and or CTRL2 CLK_SEL Reset sets the deadtime coun...

Page 802: ...T1 field descriptions Field Description 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 DTCNT1 Deadtime Count Register 1 The DTCNT1 field is used to c...

Page 803: ...edges specified by the CAPTCTRLA EDGA0 and CAPTCTRLA EDGA1 fields are ignored The software must still place a value other than 00 in either or both of the CAPTCTLRA EDGA0 and or CAPTCTRLA EDGA1 field...

Page 804: ...t capture process This bit can be cleared at any time to disable input capture operation This bit is self cleared when in one shot mode and one or more of the enabled capture circuits has had a captur...

Page 805: ...enables the edge counter which counts rising and falling edges on the PWM_B input signal 0 Edge counter disabled and held in reset 1 Edge counter enabled 6 INP_SELB Input Select B This bit selects bet...

Page 806: ...uits are enabled then capture circuit 0 is armed first after CAPTCTRLB ARMB is set Once a capture occurs capture circuit 0 is disarmed and capture circuit 1 is armed After capture circuit 1 performs a...

Page 807: ...e Capture X1 FIFO FIFO depth is 1 12 10 CX0CNT Capture X0 FIFO Word Count This field reflects the number of words in the Capture X0 FIFO FIFO depth is 1 9 8 CFXWM Capture X FIFOs Water Mark This field...

Page 808: ...rmed first after the ARMX bit is set Once a capture occurs capture circuit 0 is disarmed and capture circuit 1 is armed After capture circuit 1 performs a capture it is disarmed and capture circuit 0...

Page 809: ...0 9 8 7 6 5 4 3 2 1 0 Read CAPTVAL0 Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_SMnCVAL0 field descriptions Field Description CAPTVAL0 This read only register stores the value captured from the s...

Page 810: ...s is defined by CAPTCTRLX EDGX1 Each capture increases the value of CAPTCTRLX CX1CNT by 1 until the maximum value is reached Each read of this register decreases the value of CAPTCTRLX CX1CNT by 1 unt...

Page 811: ...MnCVAL2CYC Address 4003_3000h base 4Ah offset 96d i where i 0d to 3d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 CVAL2CYC Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_SMnCVAL2CYC field descri...

Page 812: ...ways has the value 0 CVAL3CYC This read only register stores the cycle number corresponding to the value captured in CVAL3 This register is incremented each time the counter is loaded with the INIT va...

Page 813: ...i 0d to 3d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read CAPTVAL5 Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_SMnCVAL5 field descriptions Field Description CAPTVAL5 This read only register store...

Page 814: ...value 0 11 8 PWMA_EN PWM_A Output Enables The four bits of this field enable the PWM_A outputs of submodules 3 0 respectively These bits should be set to 0 output disabled when a PWM_A pin is being u...

Page 815: ...n that updates the MASKA MASKB and MASKX fields of this register 0 Normal operation MASK bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule 1 I...

Page 816: ...3 Software Controlled Output 45 This bit is only used when DTSRCSEL SM3SEL45 is set to b10 It allows software control of which signal is supplied to the deadtime generator of that submodule 0 A logic...

Page 817: ...e generator of submodule 0 instead of PWM23 0 SM0OUT45 Submodule 0 Software Controlled Output 45 This bit is only used when DTSRCSEL SM0SEL45 is set to b10 It allows software control of which signal i...

Page 818: ...rides to the generated SM2PWM45 signal that will be passed to the deadtime logic upon the occurrence of a FORCE_OUT event in that sudeadtime logic upon the occurrence of a FORCE_OUT event in that subm...

Page 819: ...n every 4 bit field in this register each bit acts on a separate submodule Accordingly the description of every bitfield refers to the effect of an individual bit Address 4003_3000h base 188h offset 4...

Page 820: ...sor submodule counter modulus value and PWM pulse width take effect at the next PWM reload if CTRL LDMOD is clear or immediately if CTRL LDMOD is set Set the corresponding MCTRL LDOK bit by reading it...

Page 821: ...eration Resetting of the fractional delay block in case of PLL losing lock will be controlled by software 01 Not locked Monitor PLL operation to automatically disable the fractional delay block when t...

Page 822: ...the state of FSTS FFULL without regard to the state of FSTS FFPINx The PWM outputs disabled by this fault input will not be re enabled until the actual FAULTx input signal de asserts since the fault...

Page 823: ...ossible 0 PWM outputs are not re enabled at the start of a full cycle 1 PWM outputs are re enabled at the start of a full cycle FFLAG Fault Flags These read only flag is set within two CPU cycles afte...

Page 824: ...in the fault flags 0 Fault input glitch stretching is disabled 1 Input fault signals will be stretched to at least 2 IPBus clock cycles 14 11 Reserved This field is reserved This read only field is re...

Page 825: ...0 NOCOMB Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMA_FCTRL2 field descriptions Field Description 15 4 Reserved This field is reserved This read only field is reserved and always has the value 0 N...

Page 826: ...ed and latched fault signals to disable the PWM outputs 1 The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disa...

Page 827: ...ded with a user specified value which may or may not be zero If the value chosen happens to be the 2 s complement of the modulus value then the PWM generator operates in signed mode This means that if...

Page 828: ...the benefits of signed mode can be seen A common way to drive an H bridge is to use a technique called bipolar PWMs where a 50 duty cycle results in zero volts on the load Duty cycles less than 50 res...

Page 829: ...ally if ADC readings of the inverter must be scheduled near those times Phase shifting the PWM signals can open up timing windows between the switching edges to allow a signal to be sampled by the ADC...

Page 830: ...hift no DC component appears in the load voltage as long as the duty cycle of each square wave remains at 50 making this technique ideally suited for transformer loads As a result this topology is fre...

Page 831: ...g figure shows The DBLPWM signal can be run through the deadtime insertion logic VAL1 0100 VAL3 VAL5 VAL0 0000 VAL4 VAL2 INIT FF00 PWM_A DBLPWM PWM_B Figure 37 228 Double Switching Output Example 37 5...

Page 832: ...each submodule to run at a different frequency One of the options possible with this PWM module is to have one or more submodules running at a lower frequency but still synchronized to the timer in s...

Page 833: ...or one shot fashion By simply programming the desired edge of each capture circuit period and pulse width of an input signal can easily be measured without the requirement to re arm the circuit In add...

Page 834: ...However when measuring a signal that is synchronous to the PWM frequency the timer modulus range is perfectly suited for the application Consider the following figure as an example In this application...

Page 835: ...ing any interrupt latency The synchronous output switching is accomplished via a signal called FORCE_OUT This signal originates from the local FORCE bit within the submodule from submodule0 or from ex...

Page 836: ...234 shows the logic used to generate the main counter clock Each submodule can select between three clock signals the IPBus clock EXT_CLK and AUX_CLK The EXT_CLK goes to all of the submodules The AUX...

Page 837: ...eload signal from submodule0 can be broadcast as the Master Reload signal allowing the reload logic from submodule0 to control the reload of registers in other submodules 0 1 Reload Logic counts PWM c...

Page 838: ...ter initialization then the period of the counter will be locked to the register reload frequency of submodule0 Since the reload frequency is usually commensurate to the sampling frequency of the soft...

Page 839: ...r 16 bit comparator 16 bit comparator 16 bit comparator Figure 37 237 PWM Generation Hardware The generation of the Local Sync signal is performed exactly the same way as the other PWM signals in the...

Page 840: ...re possible An output compare sets the output high An output compare sets the output low An output compare generates an interrupt An output compare generates an output trigger In PWM generation an out...

Page 841: ...e SEL23 and SEL45 fields each choose from one of four signals that can be supplied to the submodule outputs the PWM signal the inverted PWM signal a binary level specified by software via the OUT23 an...

Page 842: ...independently of the other output Writing a logic zero to CTRL2 INDEP configures the PWM output as a pair of complementary channels The PWM pins are paired as shown in Figure 37 239 in complementary c...

Page 843: ...top and bottom transistor But the transistor s characteristics may make its switching off time longer than switching on time To avoid the conducting overlap of top and bottom transistors deadtime need...

Page 844: ...000 VAL2 VAL1 0100 PWM_A with deadtime PWM_A no deadtime Figure 37 241 Deadtime Insertion 37 5 2 8 1 Top Bottom Correction In complementary mode either the top or the bottom transistor controls the ou...

Page 845: ...urn off delays of each of the transistors By giving the PWM module information on which transistor is controlling at a given time this distortion can be corrected For a typical circuit in complementar...

Page 846: ...o CTRL DT values PWM_B CLK PWMX PWMB DT0 DT1 PWM_A PWMA Q D CLK Q D POSITIVE CURRENT NEGATIVE CURRENT VOLTAGE SENSOR Figure 37 243 Current status Sense Scheme for Deadtime Correction Both D flip flops...

Page 847: ...lution for the PWM period Enable the use of the fractional delay logic by setting FRCTRL FRACx_EN The FRACVALx registers act as a fractional clock cycle addition to the turn on and turn off count spec...

Page 848: ...PWM edges will dither from the nearest whole number values to achieve an average value that is equivalent to the programmed fractional value The added cycles are based on the accumulation of the fract...

Page 849: ...with that pin are used to record the edge values The following figure is a block diagram of the E Capture circuit Upon entering the pin input the signal is split into two paths One goes straight to a...

Page 850: ...l edges of the signal The type of edge to be captured by each circuit is determined by CAPTCTRLx EDGx1 and CAPTCTRLx EDGx0 whose functionality is listed in the preceding figure Also controlling the op...

Page 851: ...depending the values of OCTRL PWMxFS The fault decoder disables PWM pins selected by the fault logic and the disable mapping DISMAPn registers The following figure shows an example of the fault disabl...

Page 852: ...LT D NOCOMB2 FAULT2 DISA2 FILT D NOCOMB3 FAULT3 DISA3 Figure 37 247 Fault Decoder for PWM_A Table 37 224 Fault Mapping PWM Pin Controlling Register Bits PWM_A DISMAP0 DIS0A PWM_B DISMAP0 DIS0B PWM_X D...

Page 853: ...LAGx by writing a logic one to the bit Software clears the FIEx bit by writing a logic zero to it A reset occurs Even with the filter enabled there is a combinational path from the FAULTx inputs to th...

Page 854: ...lowing figure If FSTS FFULLx is set then the disabled PWM pins are enabled at the start of a full cycle If FSTS FHALFx is set then the disabled PWM pins are enabled at the start of a half cycle If the...

Page 855: ...l occurs at half PWM cycle boundaries while the PWM generator is engaged MCTRL RUN equals one But the OUTx bits can control the PWM pins while the PWM generator is off MCTRL RUN equals zero Thus fault...

Page 856: ...then writing a logic one to it After loading MCTRL LDOK is automatically cleared 37 5 3 2 Load Frequency CTRL LDFQ selects an integral loading frequency of one to 16 PWM reload opportunities CTRL LDFQ...

Page 857: ...ag STS RF is set Setting STS RF happens even if an actual reload is prevented by MCTRL LDOK If the PWM reload interrupt enable bit INTEN RIE is set the STS RF flag generates CPU interrupt requests all...

Page 858: ...RL RUN Note Even if MCTRL LDOK is not set setting MCTRL RUN also sets the STS RF flag To prevent a CPU interrupt request clear INTEN RIE before setting MCTRL RUN The PWM generator uses the last values...

Page 859: ...e 1 compare interrupt Compare event has occurred PWM_CAP1 SM1STS CFA1 SM1STS CFA0 SM1STS CFB1 SM1STS CFB0 SM1STS CFX1 SM1STS CFX0 SM1INTEN CFA1IE SM1INTEN CFA0IE SM1INTEN CFB1IE SM1INTEN CFB0IE SM1INT...

Page 860: ...on has been detected 37 8 DMA Each submodule can request a DMA read access for its capture FIFOs and a DMA write request for its double buffered VALx registers Table 37 226 DMA Summary DMA Request DMA...

Page 861: ...CX1DE SM2 Capture FIFO X read request SM2CVAL1 contains a value to be read SM2DMAEN CA0DE SM2 Capture FIFO A0 read request SM2CVAL2 contains a value to be read SM2DMAEN CA1DE SM2 Capture FIFO A1 read...

Page 862: ...3CVAL5 contains a value to be read SM3DMAEN CAPTDE SM3 Capture FIFO read request source select Selects source of submodule3 read DMA request Submodule 3 write request SM3DMAEN VALDE SM3VALx write requ...

Page 863: ...output trigger the PDBs 38 1 1 1 PDB0 Output Triggers Table 38 1 PDB0 output triggers Number of PDB channels 1 Number of pre triggers per PDB channel 4 PDB_ch0_out ADCA sync0 DMA_MUX source 48 FTM0_T...

Page 864: ...triggers as programmed in the FTM external trigger register EXTTRIG 1100 XBAR_OUT 38 1101 Reserved 1110 LPTMR Output 1111 Software Trigger 38 1 1 3 PDB1 Output Triggers Table 38 3 PDB1 output triggers...

Page 865: ...tion trigger and channel triggers as programmed in the FTM external trigger register EXTTRIG 1100 XBAR_OUT 41 1101 Reserved 1110 LPTMR Output 1111 Software Trigger 38 1 2 PDB s DAC External Trigger In...

Page 866: ...which can be used to trigger ADC conversion 4 times in sequence User can use the back to back feature of this chip to configure the two PDBs as a signal chain The ADC0 scan complete signal can be used...

Page 867: ...bles the ADC conversions complete to trigger the next PDB channel One programmable delay interrupt One sequence error interrupt One channel flag and one sequence error flag per pre trigger DMA support...

Page 868: ...ber of module output triggers to core is chip specific For module to core output triggers implementation see the chip configuration information 38 2 3 Back to back acknowledgment connections PDB back...

Page 869: ...LY2 POyDLY1 Pulse Generation Pulse Out y PDBPOEN y Pulse Out y DAC interval trigger x From trigger mux TOEx DAC external trigger input Control logic PDB counter DAC interval counter x Figure 38 1 PDB...

Page 870: ...ed in the modulus register and the counting is restarted This enables a continuous stream of pre triggers trigger outputs as a result of a single trigger input event Enabled Bypassed The pre trigger a...

Page 871: ...Y 32 R W 0000_0000h 38 4 14 881 4003_1198 Pulse Out n Delay register PDB1_PO1DLY 32 R W 0000_0000h 38 4 14 881 4003_119C Pulse Out n Delay register PDB1_PO2DLY 32 R W 0000_0000h 38 4 14 881 4003_11A0...

Page 872: ..._PO3DLY 32 R W 0000_0000h 38 4 14 881 38 4 1 Status and Control register PDBx_SC Address Base address 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 LDMOD PDBEIE 0 W SWTRIG Reset 0...

Page 873: ...s no effect Reading this field results 0 15 DMAEN DMA Enable When DMA is enabled the PDBIF flag generates a DMA request instead of an interrupt 0 DMA disabled 1 DMA enabled 14 12 PRESCALER Prescaler D...

Page 874: ...the IDLY register Writing zero clears this field 5 PDBIE PDB Interrupt Enable Enables the PDB interrupt When this field is set and DMAEN is cleared PDBIF generates a PDB interrupt 0 PDB interrupt dis...

Page 875: ...7 6 5 4 3 2 1 0 R 0 MOD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PDBx_MOD field descriptions Field Description 31 16 Reserved This field is reserved This read only field...

Page 876: ...n Control register 1 PDBx_CHnC1 Each PDB channel has one control register CHnC1 The fields in this register control the functionality of each PDB channel operation Address Base address 10h offset 40d...

Page 877: ...tputs Only lower M pre trigger fields are implemented in this MCU 0 PDB channel s corresponding pre trigger disabled 1 PDB channel s corresponding pre trigger enabled 38 4 6 Channel n Status register...

Page 878: ...re trigger The pre trigger asserts when the counter is equal to DLY Reading this field returns the value of internal register that is effective for the current PDB cycle 38 4 8 Channel n Delay 1 regis...

Page 879: ...is effective for the current PDB cycle 38 4 10 Channel n Delay 3 register PDBx_CHnDLY3 Address Base address 24h offset 40d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 880: ...or software trigger is selected and SWTRIG is written with 1 1 DAC external trigger input enabled DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger 0 T...

Page 881: ...his MCU 0 PDB Pulse Out disabled 1 PDB Pulse Out enabled 38 4 14 Pulse Out n Delay register PDBx_POnDLY Address Base address 194h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 882: ...lock PDB channel n pre trigger outputs 0 to M each pre trigger output is connected to ADC hardware trigger select and hardware trigger inputs The pre triggers are used to precondition the ADC block be...

Page 883: ...channel n is asserted the associated lock of the pre trigger becomes active The associated lock is released by the rising edge of the corresponding ADC_STATE EOSI1 EOSI0 the ADC_STATE EOSI1 EOSI0 sho...

Page 884: ...generate the interval triggers for DACs to update their outputs periodically DAC interval counter x is reset and started when a trigger input event occurs if DACINTCx EXT is cleared When the interval...

Page 885: ...s the value set in POyDLY DLY1 the Pulse Out goes high when the counter reaches POyDLY DLY2 it goes low POyDLY DLY2 can be set either greater or less than POyDLY DLY1 ADC pre trigger trigger outputs a...

Page 886: ...ches the MOD register value after 1 is written to SC LDOK 10 A trigger input event is detected after 1 is written to SC LDOK 11 Either the PDB counter reaches the MOD register value or a trigger input...

Page 887: ...A If SC DMAEN is set PDB can generate a DMA transfer request when SC PDBIF is set When DMA is enabled the PDB interrupt is not issued 38 6 Application information 38 6 1 Impact of using the prescaler...

Page 888: ...ed are mod 4 and so forth If the applications need a really long delay value and use a prescaler set to 128 then the resolution would be limited to 128 peripheral clock cycles Therefore use the lowest...

Page 889: ...C FTM1_C6SC FTM1_C7SC FTM1_C2V FTM1_C3V FTM1_C4V FTM1_C5V FTM1_C6V and FTM1_C7V NOTE CnSC ICRST is available only on FTM1 which has Hall sensor decoder mode FTM0 and FTM2 do not have this field 39 1 2...

Page 890: ...urce 39 1 5 FTM Fault Detection Inputs The following fault detection input options for the FTM modules are selected via the SIM_SOPT4 register The external pin option is selected by default FTM0 FAULT...

Page 891: ...input capture source options are selected via SIM_SOPTx The external pin option is selected by default FTM1 channel 0 input capture FTM1_CH0 pin or CMP0 output or CMP1 output via FTM1CH0SRC bit in SIM...

Page 892: ...together to force an output trigger This EXTTRG3 signal is connected to PDB0 channel 1011 input PDB1 channel 1011 input XBARA_IN18 and XBARB_IN6 FTM3_CH0 event output to DMAMUX source 36 FTM3_CH1 even...

Page 893: ...used as an unsigned or signed counter NOTE The number of channels supported can vary for each instance of the FTM module on a chip See the chip specific FTM information to see how many channels are s...

Page 894: ...omatically These triggers can be linked in a variety of ways during integration of the sub modules so please note the options available for used FlexTimer configuration More than one FlexTimers may be...

Page 895: ...e as pairs with equal outputs pairs with complementary outputs or independent channels with independent outputs The deadtime insertion is available for each complementary pair Generation of match trig...

Page 896: ...the MCU from Wait mode the power can then be saved by disabling FTM functions before entering Wait mode 39 2 4 Block diagram The FTM uses one input output I O pin per channel CHn FTM channel n where...

Page 897: ...V CH6IE CH6F CH1IE CH0IE CH7IE CH7F CH1F CH0F channel 0 interrupt channel 1 interrupt channel 6 interrupt channel 7 interrupt channel 7 match trigger channel 6 output signal channel 6 match trigger ch...

Page 898: ...t each FAULTj input may affect all channels selectively since FAULTM 1 0 and FAULTEN control bits are defined for each pair of channels Because there are several FAULTj inputs maximum of 4 for the FTM...

Page 899: ...n Status And Control FTM3_C1SC 32 R W 0000_0000h 39 4 6 907 4002_6018 Channel n Value FTM3_C1V 32 R W 0000_0000h 39 4 7 910 4002_601C Channel n Status And Control FTM3_C2SC 32 R W 0000_0000h 39 4 6 9...

Page 900: ...Fault Control FTM3_FLTCTRL 32 R W 0000_0000h 39 4 20 933 4002_6080 Quadrature Decoder Control And Status FTM3_QDCTRL 32 R W 0000_0000h 39 4 21 936 4002_6084 Configuration FTM3_CONF 32 R W 0000_0000h 3...

Page 901: ...nitial Value FTM0_CNTIN 32 R W 0000_0000h 39 4 8 910 4003_8050 Capture And Compare Status FTM0_STATUS 32 R W 0000_0000h 39 4 9 911 4003_8054 Features Mode Selection FTM0_MODE 32 R W 0000_0004h 39 4 10...

Page 902: ...3SC 32 R W 0000_0000h 39 4 6 907 4003_9028 Channel n Value FTM1_C3V 32 R W 0000_0000h 39 4 7 910 4003_902C Channel n Status And Control FTM1_C4SC 32 R W 0000_0000h 39 4 6 907 4003_9030 Channel n Value...

Page 903: ...trol FTM1_FLTCTRL 32 R W 0000_0000h 39 4 20 933 4003_9080 Quadrature Decoder Control And Status FTM1_QDCTRL 32 R W 0000_0000h 39 4 21 936 4003_9084 Configuration FTM1_CONF 32 R W 0000_0000h 39 4 22 93...

Page 904: ...read only field is reserved and always has the value 0 7 TOF Timer Overflow Flag Set by hardware when the FTM counter passes the value in the MOD register The TOF bit is cleared by reading the SC reg...

Page 905: ...ected This in effect disables the FTM counter 01 System clock 11 External clock PS Prescale Factor Selection Selects one of 8 division factors for the clock source selected by CLKS The new prescaler f...

Page 906: ...e MOD register latches the value into a buffer The MOD register is updated with the value of its write buffer according to Registers updated from write buffers If FTMEN 0 this write coherency mechanis...

Page 907: ...Falling Edge Only 11 Capture on Rising or Falling Edge 01 01 Output Compare Toggle Output on match 10 Clear Output on match 11 Set Output on match 1X 10 Edge Aligned PWM High true pulses clear Output...

Page 908: ...le Detected Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1 Enabled Rising and falling edges Address Base address Ch offset 8d i where i 0d to 7d Bit 31 30 29 28 27 26...

Page 909: ...n only when MODE WPDIS 1 4 MSA Channel Mode Select Used for further selections in the channel logic Its functionality is dependent on the channel mode See Table 39 8 This field is write protected It c...

Page 910: ...TMx_CnV field descriptions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 VAL Channel Value Captured FTM counter value of the input...

Page 911: ...e read of STATUS All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS Hardware sets the individual channel flags when an event occurs on the channel CHnF is cleared by rea...

Page 912: ...the register description 0 No channel event has occurred 1 A channel event has occurred 5 CH5F Channel 5 Flag See the register description 0 No channel event has occurred 1 A channel event has occurre...

Page 913: ...enable bit for FTM specific features and the control bits used to configure Fault control mode and interrupt Capture Test mode PWM synchronization Write protection Channel output initialization These...

Page 914: ...OD CnV OUTMASK and FTM counter synchronization See PWM synchronization The PWMSYNC bit configures the synchronization when SYNCMODE is 0 0 No restrictions Software and hardware triggers can be used by...

Page 915: ...ware or software triggers but not both at the same time otherwise unpredictable behavior is likely to happen The selection of the loading point CNTMAX and CNTMIN bits is intended to provide the update...

Page 916: ...1 input signal 0 Trigger is disabled 1 Trigger is enabled 4 TRIG0 PWM Synchronization Hardware Trigger 0 Enables hardware trigger 0 to the PWM synchronization Hardware trigger 0 occurs when a rising e...

Page 917: ...ing point is enabled 39 4 12 Initial State For Channels Output FTMx_OUTINIT Address Base address 5Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 918: ...Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs 0 The initialization value is 0 1 The initialization value is 1 1 CH1OI Channel 1 Ou...

Page 919: ...ly 1 Channel output is masked It is forced to its inactive state 6 CH6OM Channel 6 Output Mask Defines if the channel output is masked or unmasked 0 Channel output is not masked It continues to operat...

Page 920: ...continues to operate normally 1 Channel output is masked It is forced to its inactive state 39 4 14 Function For Linked Channels FTMx_COMBINE This register contains the control bits used to configure...

Page 921: ...configuration of the dual edge capture bits This field applies only when DECAPEN 1 DECAP bit is cleared automatically by hardware if dual edge capture one shot mode is selected and when the capture of...

Page 922: ...nly when MODE WPDIS 1 0 The deadtime insertion in this pair of channels is disabled 1 The deadtime insertion in this pair of channels is enabled 19 DECAP2 Dual Edge Capture Mode Captures For n 4 Enabl...

Page 923: ...egisters C n V and C n 1 V 0 The PWM synchronization in this pair of channels is disabled 1 The PWM synchronization in this pair of channels is enabled 12 DTEN1 Deadtime Enable For n 2 Enables the dea...

Page 924: ...ite protected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in this pair of channels is enabled 5 SYNCEN0 Synchronization Enable...

Page 925: ...mbine feature for channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 Channels n and n 1 are independent 1 Channels n and n 1 are combined 39 4 15 Deadtime Inse...

Page 926: ...a possible 63 counts This field is write protected It can be written only when MODE WPDIS 1 39 4 16 FTM External Trigger FTMx_EXTTRIG This register Indicates when a channel trigger was generated Enab...

Page 927: ...ted 6 INITTRIGEN Initialization Trigger Enable Enables the generation of the trigger when the FTM counter is equal to the CNTIN register 0 The generation of initialization trigger is disabled 1 The ge...

Page 928: ...TRIG Channel 2 Trigger Enable Enables the generation of the channel trigger when the FTM counter is equal to the CnV register 0 The generation of the channel trigger is disabled 1 The generation of th...

Page 929: ...POL4 Channel 4 Polarity Defines the polarity of the channel output This field is write protected It can be written only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity...

Page 930: ...4 18 Fault Mode Status FTMx_FMS This register contains the fault detection flags write protection enable bit and the logic OR of the enabled fault inputs Address Base address 74h offset Bit 31 30 29...

Page 931: ...the enabled fault inputs is 0 1 The logic OR of the enabled fault inputs is 1 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 FAULTF3 Fault Detection Fl...

Page 932: ...ult input 1 A fault condition was detected at the fault input 0 FAULTF0 Fault Detection Flag 0 Set by hardware when fault control is enabled the corresponding fault input is enabled and a fault condit...

Page 933: ...L Channel 1 Input Filter Selects the filter value for the channel input The filter is disabled when the value is zero CH0FVAL Channel 0 Input Filter Selects the filter value for the channel input The...

Page 934: ...n MODE WPDIS 1 0 Fault input filter is disabled 1 Fault input filter is enabled 5 FFLTR1EN Fault Input 1 Filter Enable Enables the filter for the fault input This field is write protected It can be wr...

Page 935: ...only when MODE WPDIS 1 0 Fault input is disabled 1 Fault input is enabled 0 FAULT0EN Fault Input 0 Enable Enables the fault input This field is write protected It can be written only when MODE WPDIS 1...

Page 936: ...0 0 0 FTMx_QDCTRL field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 PHAFLTREN Phase A Input Filter Enable Enables...

Page 937: ...used in the Quadrature Decoder mode 0 Phase A and phase B encoding mode 1 Count and direction encoding mode 2 QUADIR FTM Counter Direction In Quadrature Decoder Mode Indicates the counting direction 0...

Page 938: ...10 GTBEOUT Global Time Base Output Enables the global time base signal generation to other FTMs 0 A global time base signal generation is disabled 1 A global time base signal generation is enabled 9 G...

Page 939: ...R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FLT3POL FLT2POL FLT1POL FLT0POL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_FLTPOL field descriptions Field D...

Page 940: ...ault 1 The fault input polarity is active low A 0 at the fault input indicates a fault 39 4 24 Synchronization Configuration FTMx_SYNCONF This register selects the PWM synchronization configuration SW...

Page 941: ...has the value 0 12 SWSOC Software output control synchronization is activated by the software trigger 0 The software trigger does not activate the SWOCTRL register synchronization 1 The software trigg...

Page 942: ...lock 1 CNTIN register is updated with its buffer value by the PWM synchronization 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 HWTRIGMODE Hardware Tr...

Page 943: ...le 0 Inverting is disabled 1 Inverting is enabled 0 INV0EN Pair Channels 0 Inverting Enable 0 Inverting is disabled 1 Inverting is enabled 39 4 26 FTM Software Output Control FTMx_SWOCTRL This registe...

Page 944: ...ware Output Control Value 0 The software output control forces 0 to the channel output 1 The software output control forces 1 to the channel output 12 CH4OCV Channel 4 Software Output Control Value 0...

Page 945: ...rol Enable 0 The channel output is not affected by software output control 1 The channel output is affected by software output control 3 CH3OC Channel 3 Software Output Control Enable 0 The channel ou...

Page 946: ...ed This read only field is reserved and always has the value 0 9 LDOK Load Enable Enables the loading of the MOD CNTIN and CV registers with the values of their write buffers 0 Loading updated values...

Page 947: ...hing process 1 Include the channel in the matching process 1 CH1SEL Channel 1 Select 0 Do not include the channel in the matching process 1 Include the channel in the matching process 0 CH0SEL Channel...

Page 948: ...CLKS 1 0 bits may be read or written at any time Disabling the FTM counter by writing 0 0 to the CLKS 1 0 bits does not affect the FTM counter value or other registers The fixed frequency clock is an...

Page 949: ...is used by the channels either for input or output modes The FTM counter clock is the selected clock divided by the prescaler The FTM counter has these modes of operation Up counting Up down counting...

Page 950: ...x period of FTM counter clock Figure 39 169 Example of FTM up and signed counting Table 39 243 FTM counting based on CNTIN value When Then CNTIN 0x0000 The FTM counting is equivalent to TPM up countin...

Page 951: ...equirement Any values of CNTIN and MOD that do not satisfy this criteria can result in unpredictable behavior MOD CNTIN is a redundant condition In this case the FTM counter is always equal to MOD and...

Page 952: ...e final value of the count The value of CNTIN is loaded into the FTM counter and the counter increments until the value of MOD is reached at which point the counter is decremented until it returns to...

Page 953: ...n this case 0 CPWM is generated 39 5 3 3 Free running counter If FTMEN 0 and MOD 0x0000 or MOD 0xFFFF the FTM counter is a free running counter In this case the FTM counter runs free from 0x0000 throu...

Page 954: ...the TOF bit is set The NUMTOF 4 0 bits define the number of times that the FTM counter overflow should occur before the TOF bit to be set If NUMTOF 4 0 0x00 then the TOF bit is set at each FTM counter...

Page 955: ...input capture the FTMxCHn pin is an edge sensitive input ELSnB ELSnA control bits determine which edge falling or rising triggers input capture event Note that the maximum frequency for the channel in...

Page 956: ...Filter for Input Capture mode The filter function is only available on channels 0 1 2 and 3 First the input signal is synchronized by the system clock Following synchronization the input signal enter...

Page 957: ...ut The clock for the counter in the channel input filter is the system clock divided by 4 CHnFVAL 3 0 0010 binary value channel n input after the synchronizer counter filter output system clock divide...

Page 958: ...lso are reset 39 5 5 Output Compare mode The Output Compare mode is selected when DECAPEN 0 COMBINE 0 CPWMS 0 and MSnB MSnA 0 1 In Output Compare mode the FTM can generate timed pulses with programmab...

Page 959: ...de when the match clears the channel output channel n output CHnF bit TOF bit CNT MOD 0x0005 CnV 0x0003 counter overflow channel n match counter overflow channel n match counter overflow 0 1 2 3 4 5 0...

Page 960: ...ches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by FTM If ELSnB ELSnA 1 0 then the channel n o...

Page 961: ...different from zero the following EPWM signals can be generated 0 EPWM signal if CnV CNTIN EPWM signal between 0 and 100 if CNTIN CnV MOD 100 EPWM signal when CNTIN CnV or CnV MOD 39 5 7 Center Align...

Page 962: ...B ELSnA 0 0 when the FTM counter reaches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by FTM If...

Page 963: ...do not need to generate a 100 duty cycle CPWM signal This is not a significant limitation because the resulting period is much longer than required for normal applications The CPWM mode must not be us...

Page 964: ...n the generation of the channels n and n 1 output However if ELSnB ELSnA 0 0 then the channel n output is not controlled by FTM and if ELS n 1 B ELS n 1 A 0 0 then the channel n 1 output is not contro...

Page 965: ...LSnA X 1 MOD C n V CNTIN Figure 39 192 Channel n output if C n V CNTIN and CNTIN C n 1 V MOD FTM counter not fully 100 duty cycle channel n output with ELSnB ELSnA 1 0 not fully 0 duty cycle channel n...

Page 966: ...C n V CNTIN and CNTIN C n 1 V MOD and C n 1 V is Almost Equal to MOD FTM counter 0 duty cycle channel n output with ELSnB ELSnA 1 0 100 duty cycle channel n output with ELSnB ELSnA X 1 C n V MOD CNTIN...

Page 967: ...annel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle 0 duty cycle MOD Figure 39 197 Channel n output if C n V C n 1 V CNTIN FTM counter CNTIN channel n output with...

Page 968: ...nnel n output if CNTIN C n V MOD and CNTIN C n 1 V MOD and C n V C n 1 V FTM counter C n V channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 0 duty cycle 100 duty cycle MOD C...

Page 969: ...1 V CNTIN and CNTIN C n V MOD FTM counter channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle 0 duty cycle MOD C n V C n 1 V CNTIN Figure 39 202 Channel n outpu...

Page 970: ...Channel n output if C n 1 V MOD and CNTIN C n V MOD 39 5 8 1 Asymmetrical PWM In Combine mode the control of the PWM signal first edge when the channel n match occurs that is FTM counter C n V is ind...

Page 971: ...annel n match Figure 39 205 Channel n 1 output in Complementary mode with ELSnB ELSnA 1 0 FTM counter channel n 1 match channel n 1 output with COMP 1 channel n 1 output with COMP 0 channel n output w...

Page 972: ...ode is not CPWM then MOD register is updated after MOD register was written and the FTM counter changes from MOD to CNTIN If the FTM counter is at free running counter mode then this update occurs whe...

Page 973: ...pdated by the C n V and C n 1 V register synchronization If the selected mode is not output compare and SYNCEN 1 then CnV register is updated by the C n V and C n 1 V register synchronization 39 5 11...

Page 974: ...t occurs when 1 is written to the SYNC SWSYNC bit The SWSYNC bit is cleared when 0 is written to it or when the PWM synchronization initiated by the software event is completed If another software tri...

Page 975: ...lue CNTIN If in Up down counting mode then the boundary cycle is defined as when the counter turns from down to up counting and when from up to down counting The following figure shows the boundary cy...

Page 976: ...ue This synchronization is enabled if FTMEN 1 The MOD register synchronization can be done by either the enhanced PWM synchronization SYNCMODE 1 or the legacy PWM synchronization SYNCMODE 0 However it...

Page 977: ...wait hardware trigger n HWTRIGMODE bit clear TRIGn bit wait the next selected loading point update MOD with its buffer value update MOD with its buffer value HWRSTCNT bit Figure 39 210 MOD register sy...

Page 978: ...r is updated write 1 to TRIG0 bit TRIG0 bit trigger 0 event Figure 39 212 MOD synchronization with SYNCMODE 0 HWTRIGMODE 0 PWMSYNC 0 REINIT 0 and a hardware trigger was used If SYNCMODE 0 PWMSYNC 0 an...

Page 979: ...SYNC 0 REINIT 1 and a hardware trigger was used If SYNCMODE 0 and PWMSYNC 1 then this synchronization is made on the next selected loading point after the software trigger event takes place The SWSYNC...

Page 980: ...ization mechanism is the same as the MOD register synchronization However it is expected that the C n V and C n 1 V registers be synchronized only by the enhanced PWM synchronization SYNCMODE 1 39 5 1...

Page 981: ...gger n TRIGn bit HWOM bit SWOM bit SWSYNC bit rising edge of system clock update OUTMASK with its buffer value hardware trigger OUTMASK is updated by software trigger OUTMASK is updated by hardware tr...

Page 982: ...SWSYNC bit software trigger event Figure 39 217 OUTMASK synchronization with SYNCMODE 0 SYNCHOM 1 PWMSYNC 0 and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OU...

Page 983: ...TRL register synchronization updates the INVCTRL register with its buffer value The INVCTRL register can be updated at each rising edge of system clock INVC 0 or by the enhanced PWM synchronization IN...

Page 984: ...bit rising edge of system clock update INVCTRL with its buffer value update INVCTRL with its buffer value HWINVC bit TRIGn bit wait hardware trigger n update INVCTRL with its buffer value HWTRIGMODE b...

Page 985: ...CTRL is updated by hardware trigger enhanced PWM synchronization update SWOCTRL register by PWM synchronization update SWOCTRL register at each rising edge of system clock yes 0 1 0 0 no 1 SWOC bit SY...

Page 986: ...l output from transitioning to 1 If no deadtime insertion is selected then the channel n 1 transitions to logical value 1 immediately after the synchronization event occurs synchronization event chann...

Page 987: ...e trigger TRIGn bit 0 0 0 0 0 1 Figure 39 223 FTM counter synchronization flowchart In the case of legacy PWM synchronization the FTM counter synchronization depends on REINIT and PWMSYNC bits accordi...

Page 988: ...FTM counter synchronization with SYNCMODE 0 HWTRIGMODE 0 REINIT 1 PWMSYNC 0 and a hardware trigger was used If SYNCMODE 0 REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enabled...

Page 989: ...ed the channel n output behavior is changed to force high at the beginning of the PWM period force low at the channel n match and force high at the channel n 1 match See the following figure NOTE chan...

Page 990: ...INVCTRL register synchronization INV m bit channel n output after the inverting channel n 1 output after the inverting INV m bit selects the inverting to the pair channels n and n 1 channel n output b...

Page 991: ...OCV 1 and CH n 1 OCV 0 SWOCTRL register synchronization SWOCTRL register synchronization write to SWOCTRL register write to SWOCTRL register Figure 39 229 Example of software output control in Combin...

Page 992: ...he DTPS 1 0 bits define the prescaler for the system clock and the DTVAL 5 0 bits define the deadtime modulo that is the number of the deadtime prescaler clocks The deadtime delay insertion ensures th...

Page 993: ...39 230 Deadtime insertion with ELSnB ELSnA 1 0 POL n 0 and POL n 1 0 FTM counter channel n 1 match channel n output before deadtime insertion channel n 1 output before deadtime insertion channel n ou...

Page 994: ...Although in most cases the deadtime delay is not comparable to channels n and n 1 duty cycle the following figures show examples where the deadtime delay is comparable to the duty cycle FTM counter ch...

Page 995: ...k The output mask can be used to force channels output to their inactive state through software For example to control a BLDC motor Any write to the OUTMASK register updates its write buffer The OUTMA...

Page 996: ...e 39 5 16 Fault control The fault control is enabled if FAULTM 1 0 0 0 FTM can have up to four fault inputs FAULTnEN bit where n 0 1 2 3 enables the fault input n and FFLTRnEN bit enables the fault in...

Page 997: ...0 and FAULTnEN 1 then the fault input n signal is delayed 3 FFVAL 3 0 rising edges of the system clock that is the FAULTFn bit is set 4 FFVAL 3 0 rising edges of the system clock after a rising edge o...

Page 998: ...Automatic fault clearing If the automatic fault clearing is selected FAULTM 1 0 1 1 then the channels output disabled by fault control is again enabled when the fault input signal FAULTIN returns to z...

Page 999: ...he fault control with manual fault clearing and POLn 0 NOTE Figure 39 238 Fault control with manual fault clearing 39 5 16 3 Fault inputs polarity control The FLTjPOL bit selects the fault input j pol...

Page 1000: ...l n 1 Output 0 0 is forced to zero is forced to zero 0 1 is forced to zero is forced to one 1 0 is forced to one is forced to zero 1 1 is forced to one is forced to one The following table shows the v...

Page 1001: ...tput signal CH n OI CH n 1 OI COMP m INV m EN CH n OC CH n OCV CH n 1 OC CH n 1 OCV DTEN m CH n OM CH n 1 OM FAULTEN m POL n POL n 1 Figure 39 239 Priority of the features used at the generation of ch...

Page 1002: ...RIG 1 CH4TRIG 1 CH5TRIG 1 the beginning of new PWM cycles MOD FTM counter C5V FTM counter C4V FTM counter C3V FTM counter C2V FTM counter C1V FTM counter C0V CNTIN a b c d Figure 39 240 Channel match...

Page 1003: ...unting achieves the CNTIN register value CPWMS 0 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06 initialization trigger write to CNT FTM counter system clock CNTIN 0x0000 MOD 0x000F Figure 39 242 In...

Page 1004: ...24 0x23 0x22 0x21 0x20 initialization trigger Figure 39 245 Initialization trigger is generated if the channel n is in Input Capture mode ICRST 1 and the selected input capture event occurs in the cha...

Page 1005: ...1 CPWMS 0 CNTIN 0x0000 and MOD 0xFFFF FTM channel n configuration input capture mode DECAPEN 0 COMBINE 0 and MSnB MSnA 0 0 0x0300 0x78AC set CAPTEST clear CAPTEST write 0x78AC 0x1056 0x1053 0x1055 0x1...

Page 1006: ...5 24 Dual Edge Capture mode The Dual Edge Capture mode is selected if DECAPEN 1 This mode allows to measure a pulse width or period of the signal on the input of channel n of a channel pair The channe...

Page 1007: ...edge by channel n 1 is detected at channel n input In this mode a coherency mechanism ensures coherent data when the C n V and C n 1 V registers are read The only requirement is that C n V must be rea...

Page 1008: ...The latest captured values are always available in these registers even after the DECAP bit is cleared In this mode it is possible to clear only the CH n 1 F bit Therefore when the CH n 1 F bit is se...

Page 1009: ...4 9 11 12 13 14 9 10 7 8 15 16 17 18 19 20 21 22 23 24 25 26 27 28 15 16 19 20 22 24 Problem 1 channel n input 1 set DECAP not clear CH n F and clear CH n 1 F Problem 2 channel n input 1 set DECAP no...

Page 1010: ...F bit clear CH n F 1 8 12 22 24 11 19 21 23 Figure 39 249 Dual Edge Capture Continuous mode for positive polarity pulse width measurement 39 5 24 4 Period measurement If the channels n and n 1 are con...

Page 1011: ...C n 1 V registers are ready for reading channel n input after the filter DECAPEN bit C n 1 V FTM counter clear CH n 1 F problem 2 2 1 2 3 channel input DECAP bit set DECAPEN set DECAP 5 6 7 8 10 3 4 6...

Page 1012: ...FTM counter clear CH n 1 F 2 1 2 3 channel input DECAP bit set DECAPEN set DECAP 5 6 7 8 10 3 4 6 5 Note The commands set DECAPEN set DECAP clear CH n F and clear CH n 1 F are made by the user 4 9 11...

Page 1013: ...ansferred to C n 1 V register when the C n V register is read In the following figure the read of C n V returns the FTM counter value when the event 1 occurred and the read of C n 1 V returns the FTM...

Page 1014: ...ts in FILTER0 register The phase B input filter is enabled by PHBFLTREN bit and this filter s value is defined by CH1FVAL 3 0 bits CH n 1 FVAL 3 0 bits in FILTER0 register Except for CH0FVAL 3 0 and C...

Page 1015: ...and B signals define the counting rate The FTM counter is updated when there is an edge either at the phase A or phase B signals If PHAPOL 0 and PHBPOL 0 then the FTM counter increment happens when t...

Page 1016: ...M counter overflow occurred phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1 1 set TOF set TOFDIR set TOF set TOFDIR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figu...

Page 1017: ...ature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications phase A phase B FTM counter MOD CNTIN 0x0000 T...

Page 1018: ...void these oscillations 39 5 26 BDM mode When the chip is in BDM mode the BDMMODE 1 0 bits select the behavior of the FTM counter the CH n F bit the channels output and the writes to the MOD CNTIN and...

Page 1019: ...hannels outputs are updated to the initial value except for channels in Output Compare mode In the channels outputs initialization the channel n output is forced to the CH n OI bit value when the valu...

Page 1020: ...EL 0 CH4SEL 1 CH5SEL 0 CH6SEL 1 CH7SEL 0 f LDOK 1 CH0SEL 1 CH1SEL 1 CH2SEL 1 CH3SEL 1 CH4SEL 1 CH5SEL 1 CH6SEL 1 CH7SEL 1 d e f b a FTM counter MOD FTM counter C7V FTM counter C6V FTM counter C5V FTM...

Page 1021: ...ilable on channel j output If CHjIE 1 then the channel j interrupt is generated when the channel j match occurs At the intermediate load neither the channels outputs nor the FTM counter are changed So...

Page 1022: ...les the configuration of each FTM module should guarantee that its FTM counter starts counting as soon as the gtb_in signal is 1 The GTB feature does not provide continuous synchronization of FTM coun...

Page 1023: ...r its value is updated to zero and the pins are not controlled by FTM See the table in the description of CnSC register After the reset the FTM should be configurated item 2 It is necessary to define...

Page 1024: ...ere is a write to CNT register item 3 In this case use the software output control Software output control or the initialization Initialization to update the channel output to the selected value item...

Page 1025: ...e in the safe value Re Configuration FTM counter and channels to generation of periodic signals Disable the clock If the selected mode is Quadrature Decoder then disable this mode Examples of the re c...

Page 1026: ...is necessary SWSOC 0 1 and SWOC 0 1 SW Synchronization for Inverting if it is necessary SWINVC 0 1 and INVC 0 1 SW Synchronization for SWOM always SWOM 1 No enable the SW Synchronization for write buf...

Page 1027: ...40 1 2 PIT Trigger Output Assignments The PIT timer channels are used to trigger other peripheral events such as ADC acquisitions or DMA transfers On this device the following assignments have been m...

Page 1028: ...er 1 PIT registers Peripheral bus load_value PIT Triggers Peripheral bus clock Interrupts Figure 40 1 Block diagram of the PIT NOTE See the chip specific PIT information for the number of PIT channels...

Page 1029: ...egister PIT_TFLG0 32 R W 0000_0000h 40 4 5 1033 4003_7110 Timer Load Value Register PIT_LDVAL1 32 R W 0000_0000h 40 4 2 1031 4003_7114 Current Timer Value Register PIT_CVAL1 32 R 0000_0000h 40 4 3 103...

Page 1030: ...DIS FRZ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 PIT_MCR field descriptions Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 Reserved...

Page 1031: ...will count down until it reaches 0 then it will generate an interrupt and load this register value again Writing a new value to this register will not restart the timer instead the value will be loade...

Page 1032: ...tions Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 CHN Chain Mode When activated Timer n 1 needs to expire before timer n can de...

Page 1033: ...value 0 0 TIF Timer Interrupt Flag Sets to 1 at the end of the timer period Writing 1 to this flag clears it Writing 0 has no effect If enabled or when TCTRLn TIE 1 TIF causes an interrupt request 0 T...

Page 1034: ...imer with TCTRLn TEN See the following figure p1 Timer enabled Disable timer p1 p1 Start value p1 Trigger event p1 Re enable timer Figure 40 23 Stopping and starting a timer The counter period of a ru...

Page 1035: ...rrupts can be enabled by setting TCTRLn TIE TFLGn TIF are set to 1 when a timeout occurs on the associated timer and are cleared to 0 by writing a 1 to the corresponding TFLGn TIF 40 5 3 Chained timer...

Page 1036: ...EN Timer 3 shall be used only for triggering Therefore Timer 3 is started by writing a 1 to TCTRL3 TEN TCTRL3 TIE stays at 0 The following example code matches the described setup turn on PIT PIT_MCR...

Page 1037: ...enabled by setting TCTRL2 TIE the Chain mode is activated by setting TCTRL2 CHN and the timer is started by writing a 1 to TCTRL2 TEN TCTRL1 TEN needs to be set and TCTRL1 CHN and TCTRL1 TIE are clear...

Page 1038: ...Example configuration for chained timers KV4x Reference Manual Rev 2 02 2015 1038 Preliminary Freescale Semiconductor Inc...

Page 1039: ...ntended incremenatal position sensor for motor control The following table shows how these modules are configured This adheres to Kinetis K series FTM instantiations Table 41 1 ENC Signal Assignment E...

Page 1040: ...m count frequency equals the peripheral clock rate Position counter can be initialized by software or external events Preloadable 16 bit revolution counter Inputs can be connected to a general purpose...

Page 1041: ...ure Decoder Block Diagram 41 2 3 System Block Diagram The following figure shows the block diagram of the quadrature decoder module integrated into an SoC XBAR PHASEA PHASEB INDEX HOME FILTER TIMER 4...

Page 1042: ...osition difference counter 41 2 6 Position Counter The 32 bit position counter calculates up or down on every count pulse generated by the difference of PHASEA and PHASEB This counter acts as an integ...

Page 1043: ...r is read the position difference of the counter s contents is copied into the position difference hold register POSDH and the position difference counter is cleared 41 2 9 Revolution Counter The 16 b...

Page 1044: ...ting in the positive direction PHASEA is the trailing phase for a shaft rotating in the negative direction It can also be used as the single input when the quadrature decoder module is used as a singl...

Page 1045: ...has reached a defined home position This general purpose signal can also be connected to the timer module via the Crossbar module XBAR 41 3 5 Trigger Input TRIGGER The TRIGGER input can be used to cle...

Page 1046: ...d Register ENC_REVH 16 R 0000h 41 4 7 1052 4005_500E Upper Position Counter Register ENC_UPOS 16 R W 0000h 41 4 8 1052 4005_5010 Lower Position Counter Register ENC_LPOS 16 R W 0000h 41 4 9 1053 4005_...

Page 1047: ...Disable HOME interrupts 1 Enable HOME interrupts 13 HIP Enable HOME to Initialize Position Counters UPOS and LPOS This read write bit allows the position counter to be initialized by the HOME signal 0...

Page 1048: ...red 1 INDEX pulse interrupt has occurred 7 XIE INDEX Pulse Interrupt Enable This read write bit enables index interrupts 0 INDEX pulse interrupt is disabled 1 INDEX pulse interrupt is enabled 6 XIP IN...

Page 1049: ...than the period of the expected noise This way a noise spike will only corrupt one sample The FILT_CNT value should be chosen to reduce the probablility of noisy samples causing an incorrect transiti...

Page 1050: ...A value of 0x0 represents 3 samples A value of 0x7 represents 10 samples The value of FILT_CNT affects the input latency FILT_PER Input Filter Sample Period These bits represent the sampling period in...

Page 1051: ...unt pulse This counter acts as a differentiator whose count value is proportional to the change in position since the last time the position counter was read When the position register the position di...

Page 1052: ...t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENC_REVH field descriptions Field Description REVH This read only register contains a snapshot of the value of the REV register 41 4 8 Upper Position Counter Register...

Page 1053: ...005_5012h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read POSH 31 16 Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENC_UPOSH field descriptions Field Description POSH 31 16 This read only register contai...

Page 1054: ...ize the upper half of the position counter UPOS 41 4 13 Lower Initialization Register ENC_LINIT Address 4005_5000h base 18h offset 4005_5018h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read INIT 15 0 W...

Page 1055: ...0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read FPHA FPHB FIND FHOM PHA PHB INDEX HOME Write Reset 0 0 0 0 0 0 0 0 ENC_IMR field descriptions Field Description 15 8 Reserved This field is reserved This read only fie...

Page 1056: ...e 1Ch offset 4005_501Ch Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TEN TCE QDN TEST_PERIOD TEST_COUNT Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENC_TST field descriptions Field Description 15 TE...

Page 1057: ...B Change Interrupt Enable This read write bit enables simultaneous PHASEA and PHASEB change interrupts based on SABIRQ being set 0 Simultaneous PHASEA and PHASEB change interrupt disabled 1 Simultaneo...

Page 1058: ...ount Direction Flag This read only flag is used to indicate the direction of the last count 0 Last count was in the down direction 1 Last count was in the up direction 2 MOD Enable Modulo Counting Whe...

Page 1059: ...0 ENC_UMOD field descriptions Field Description MOD 31 16 This read write register contains the upper most significant half of the modulus register MOD acts as the upper bound during modulo counting...

Page 1060: ...ase 26h offset 4005_5026h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read COMP 15 0 Write Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ENC_LCOMP field descriptions Field Description COMP 15 0 This read write...

Page 1061: ...culating speed For applications with slow motor speeds and low line count quadrature encoders the timer module enables high resolution velocity measurements by measuring the time period between quadra...

Page 1062: ...er CTRL XIP or CTRL HIP can enable the position counter to be initialized in response to a HOME or INDEX signal transition 41 6 Resets There are no special requirements This module is reset by any sys...

Page 1063: ...SR PCS Prescaler glitch filter clock number Chip clock 00 0 MCGIRCLK internal reference clock not available in VLPS VLLS modes 01 1 LPO 1 kHz clock not available in VLLS0 mode 10 2 ERCLK32K secondary...

Page 1064: ...us wakeup from any low power mode Hardware trigger output Counter supports free running mode or reset on compare Configurable clock source for prescaler glitch filter Configurable input source for pul...

Page 1065: ...can select one of the input pins to be used in Pulse Counter mode State meaning Assertion If configured for pulse counter mode with active high input then assertion causes the CNR to increment Deasse...

Page 1066: ...ed This read only field is reserved and always has the value 0 7 TCF Timer Compare Flag TCF is set when the LPTMR is enabled and the CNR equals the CMR and increments TCF is cleared when the LPTMR is...

Page 1067: ...t whenever TCF is set 1 CNR is reset on overflow 1 TMS Timer Mode Select Configures the mode of the LPTMR TMS must be altered only when the LPTMR is disabled 0 Time Counter mode 1 Pulse Counter mode 0...

Page 1068: ...clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges 1010 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 risi...

Page 1069: ...When the LPTMR is enabled and the CNR equals the value in the CMR and increments TCF is set and the hardware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigger...

Page 1070: ...the four clocks The clock source must be enabled before the LPTMR is enabled NOTE The clock source selected need to be configured to remain enabled in low power modes otherwise the LPTMR will not ope...

Page 1071: ...filter directly clocks the CNR When the LPTMR is first enabled the output of the glitch filter is asserted that is logic 1 for active high and logic 0 for active low The following table shows the chan...

Page 1072: ...rescaler output in Time Counter mode with prescaler enabled Input source assertion in Pulse Counter mode with glitch filter bypassed Glitch filter output in Pulse Counter mode with glitch filter enabl...

Page 1073: ...will assert on each compare and deassert on the following increment of the CNR 42 5 7 LPTMR interrupt The LPTMR interrupt is generated whenever CSR TIE and CSR TCF are set CSR TCF is cleared by disab...

Page 1074: ...Functional description KV4x Reference Manual Rev 2 02 2015 1074 Preliminary Freescale Semiconductor Inc...

Page 1075: ...ed CAN bus Routing of the wakeup source to either the synchronous Doze or asynchronous Stop wakeup path within the FlexCAN module The reference clock for the glitch filter is a 4 MHz clock derived fro...

Page 1076: ...CAN 2 0 B protocol specifications A general block diagram is shown in the following figure which describes the main subblocks implemented in the FlexCAN module including one associated memory for stor...

Page 1077: ...ield Real time processing Reliable operation in the EMI environment of a vehicle Cost effectiveness Required bandwidth The FlexCAN module is a full implementation of the CAN protocol specification the...

Page 1078: ...ures The FlexCAN module includes these distinctive features Full implementation of the CAN protocol specification Version 2 0 B Standard data frames Extended data frames Zero to eight bytes data lengt...

Page 1079: ...us activity Remote request frames may be handled automatically or by software CAN bit time settings and configuration bits can only be written in Freeze mode Tx mailbox status Lowest priority buffer o...

Page 1080: ...output of the transmitter is internally fed back to the receiver input The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state logic 1 FlexCAN behaves as it normally does wh...

Page 1081: ...re information Stop mode This low power mode is entered when Stop mode is requested at MCU level and the LPM_ACK bit in the MCR Register is asserted by the FlexCAN When in Stop Mode the module puts it...

Page 1082: ...red to have either Supervisor or Unrestricted access by programming the SUPV field in the MCR register These registers are identified as S U in the Access column of Table 43 2 Table 43 2 Register acce...

Page 1083: ...4 4 1096 4002_4010 Rx Mailboxes Global Mask Register CAN0_RXMGMASK 32 R W Undefined 43 4 5 1097 4002_4014 Rx 14 Mask register CAN0_RX14MASK 32 R W Undefined 43 4 6 1098 4002_4018 Rx 15 Mask register...

Page 1084: ...ual Mask Registers CAN0_RXIMR10 32 R W Undefined 43 4 18 1120 4002_48AC Rx Individual Mask Registers CAN0_RXIMR11 32 R W Undefined 43 4 18 1120 4002_48B0 Rx Individual Mask Registers CAN0_RXIMR12 32 R...

Page 1085: ...egisters CAN1_RXIMR2 32 R W Undefined 43 4 18 1120 4002_588C Rx Individual Mask Registers CAN1_RXIMR3 32 R W Undefined 43 4 18 1120 4002_5890 Rx Individual Mask Registers CAN1_RXIMR4 32 R W Undefined...

Page 1086: ...e Section page 4002_58B8 Rx Individual Mask Registers CAN1_RXIMR14 32 R W Undefined 43 4 18 1120 4002_58BC Rx Individual Mask Registers CAN1_RXIMR15 32 R W Undefined 43 4 18 1120 Memory map register d...

Page 1087: ...onfiguration Address Base address 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R MDIS FRZ RFEN HALT NOTRDY WAKMSK SOFTRST FRZACK SUPV SLFWAK WRNEN LPMACK WAKSRC DOZE SRXDIS IRMQ W Res...

Page 1088: ...detected and NCEFAFRZ bit in CAN_MECR register is asserted 0 Not enabled to enter Freeze mode 1 Enabled to enter Freeze mode 29 RFEN Rx FIFO Enable This bit controls whether the Rx FIFO feature is ena...

Page 1089: ...follow a request acknowledge procedure across clock domains it may take some time to fully propagate its effect The SOFTRST bit remains asserted while reset is pending and is automatically negated whe...

Page 1090: ...nables the generation of the TWRNINT and RWRNINT flags in the Error and Status Register 1 ESR1 If WRNEN is negated the TWRNINT and RWRNINT flags will always be zero independent of the values of the er...

Page 1091: ...hardware in other modes 0 Individual Rx masking and queue feature are disabled For backward compatibility with legacy applications the reading of C S word locks the MB even if it is EMPTY 1 Individua...

Page 1092: ...One full ID standard and extended per ID Filter Table element 01 Format B Two full standard IDs or two partial 14 bit standard and extended IDs per ID Filter Table element 10 Format C Four partial 8...

Page 1093: ...fields of CAN_CTRL1 become read only The contents of this register are not affected by soft reset NOTE The CAN bit variables in CAN_CTRL1 and in CAN_CBT are stored in the same register Address Base a...

Page 1094: ...by hardware in other modes Phase Buffer Segment 2 PSEG2 1 Time Quanta 15 BOFFMSK Bus Off Interrupt Mask This bit provides a mask for the Bus Off Interrupt BOFFINT in CAN_ESR1 register 0 Bus Off interr...

Page 1095: ...de of CAN bits at the Rx input It can be written in Freeze mode only because it is blocked by hardware in other modes NOTE For proper operation to assert SMP it is necessary to guarantee a minimum val...

Page 1096: ...ode transmission is disabled all error counters described in CAN_ECR register are frozen and the module operates in a CAN Error Passive mode Only messages acknowledged by another CAN station will be r...

Page 1097: ...in the first Mailbox then the write value is discarded Reading this register affects the Mailbox Unlocking procedure see Section Mailbox Lock Mechanism Address Base address 8h offset Bit 31 30 29 28 2...

Page 1098: ...G bits mask each Mailbox filter field SMB RTR 1 CAN_CTRL2 RRS CAN_CTRL2 EACEN Mailbox filter fields MB RTR MB IDE MB ID Reserved 0 0 note 2 note 3 MG 28 0 MG 31 29 0 1 MG 31 MG 30 MG 28 0 MG 29 1 0 MG...

Page 1099: ...n the filter is don t care 1 The corresponding bit in the filter is checked 43 4 7 Rx 15 Mask register CANx_RX15MASK This register is located in RAM RX15MASK is provided for legacy application support...

Page 1100: ...eflect Error Passive state If the FlexCAN state is Error Passive and either TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the other already satisfies this condition the FL...

Page 1101: ...23 16 Reserved This field is reserved 15 8 RXERRCNT Receive Error Counter Receive Error Counter for all errors detected in received messages The RXERRCNT counter is read only except in Freeze mode wh...

Page 1102: ...errupt request Write 1 to clear the ERR_OVR bit if it is set Starting from all error flags cleared a first error event sets the ERRINT provided the corresponding mask bit is asserted If other error ev...

Page 1103: ...Reserved Reserved 0 Reserved Reserved Reserved 0 ERROVR Reserved BOFFDONEINT SYNCH TWRNINT RWRNINT W w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 43 Flex Controller Area Network Flex...

Page 1104: ...d only field is reserved and always has the value 0 28 Reserved This field is reserved 27 Reserved This field is reserved 26 Reserved This field is reserved 25 22 Reserved This field is reserved This...

Page 1105: ...ked CPU must clear this flag before disabling the bit Otherwise it will be set when the WRNEN is set again Writing 0 has no effect This flag is not generated during Bus Off state This bit is not updat...

Page 1106: ...bit 0 No such occurrence 1 A Form Error occurred since last read of this register 10 STFERR Stuffing Error This bit indicates that a Stuffing Error has been detected by the receiver node 0 No such oc...

Page 1107: ...terrupt This bit is set when FlexCAN enters Bus Off state If the corresponding mask bit in the Control Register 1 CAN_CTRL1 BOFFMSK is set an interrupt is generated to the CPU This bit is cleared by w...

Page 1108: ...ield Description BUF31TO0M Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB31 to MB0 NOTE Setting or clearing a bit in the CAN_IMASK1 Register ca...

Page 1109: ...DMA feature for Rx FIFO enabled the function of the 8 least significant interrupt flags BUF7I BUF0I are changed to support the DMA operation BUF7I and BUF6I are not used as well as BUF4I to BUF1I BUF...

Page 1110: ...1 1 MB7 completed transmission reception when MCR RFEN 0 or Rx FIFO overflow when MCR RFEN 1 6 BUF6I Buffer MB6 Interrupt Or Rx FIFO Warning When the RFEN bit in the CAN_MCR register is cleared Rx FI...

Page 1111: ...hen MCR RFEN 0 1 The corresponding buffer has successfully completed transmission or reception when MCR RFEN 0 0 BUF0I Buffer MB0 Interrupt Or Clear FIFO bit When the RFEN bit in MCR is cleared Rx FIF...

Page 1112: ...ield defines the number of Rx FIFO filters as shown in the following table The maximum selectable number of filters is determined by the MCU This field can only be written in Freeze mode as it is bloc...

Page 1113: ...6 39 0x5 48 MB 0 17 MB 18 63 Elements 0 17 Elements 18 47 0x6 56 MB 0 19 MB 20 63 Elements 0 19 Elements 20 55 0x7 64 MB 0 21 MB 22 63 Elements 0 21 Elements 22 63 0x8 72 MB 0 23 MB 24 63 Elements 0 2...

Page 1114: ...bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process This bit does not affect matching for Rx FIFO This bit can be written only in Freeze mode b...

Page 1115: ...erved This field is reserved This read only field is reserved and always has the value 0 14 VPS Valid Priority Status This bit indicates whether CAN_ESR2 IMB and CAN_ESR2 LPTM contents are currently v...

Page 1116: ...s the value 0 43 4 14 CRC Register CANx_CRCR This register provides information about the CRC of transmitted messages This register is updated at the same time the Tx Interrupt Flag is asserted Addres...

Page 1117: ...rfect alignment The following table shows how the FGM bits correspond to each IDAF field Rx FIFO ID Filter Table Elements Format CAN_MCR ID AM Identifier Acceptance Filter Fields RTR IDE RXIDA RXIDB 1...

Page 1118: ...has the value 0 IDHIT Identifier Acceptance Filter Hit Indicator This field indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Rx FIFO If multipl...

Page 1119: ...BT BTF bit is asserted otherwise it has no effect It extends the CAN_CTRL1 PRESDIV value range The Sclock period defines the time quantum of the CAN protocol For the reset value the Sclock frequency i...

Page 1120: ...e range This field can be written only in Freeze mode because it is blocked by hardware in other modes Phase Buffer Segment 1 EPSEG2 1 Time Quanta Time Quantum one Sclock period 43 4 18 Rx Individual...

Page 1121: ...ng bit in the filter is checked 43 4 53 Message buffer structure The message buffer structure used by the FlexCAN module is represented in the following figure Both Extended 29 bit identifier and Stan...

Page 1122: ...field is automatically updated to FULL 0b0010 FULL MB is full FULL Yes FULL The act of reading the C S word followed by unlocking the MB SRV does not make the code return to EMPTY It remains FULL If...

Page 1123: ...ANSWER 0b1110 0 A Remote Answer was configured to recognize a remote request frame received After that an MB is set to transmit a response frame The code is automatically changed to TANSWER 0b1110 See...

Page 1124: ...NACTIVE MB does not participate in arbitration process 0b1001 ABORT MB is aborted ABORT MB does not participate in arbitration process 0b1100 DATA MB is a Tx Data Frame MB RTR must be 0 DATA 0 INACTIV...

Page 1125: ...andard or extended 1 Frame format is extended 0 Frame format is standard RTR Remote Transmission Request This bit affects the behavior of remote frames and is part of the reception filter See Table 43...

Page 1126: ...This 3 bit field is used only when LPRIO_EN bit is set in CAN_MCR and it only makes sense for Tx mailboxes These bits are not transmitted They are appended to the regular ID to define the transmissio...

Page 1127: ...tains the ID filter table configurable from 8 to 40 table elements that specifies filtering criteria for accepting frames into the FIFO Out of reset the ID filter table flexible memory area defaults t...

Page 1128: ...nded 29 1 B RTR IDE RXIDB_0 standard 29 19 extended 29 16 RTR IDE RXIDB_1 standard 13 3 extended 13 0 C RXIDC_0 std ext 31 24 RXIDC_1 std ext 23 16 RXIDC_2 std ext 15 8 RXIDC_3 std ext 7 0 Unimplement...

Page 1129: ...cription The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames The mailbox system is composed by a set of Message Buffers MB that st...

Page 1130: ...aborted or transmitted see Transmission abort mechanism If backwards compatibility is desired CAN_MCR AEN bit is negated just write the INACTIVE code 0b1000 to the CODE field to inactivate the MB but...

Page 1131: ...or Delimiter field of a CAN frame During the Overload Delimiter field of a CAN frame When the winner is inactivated and the CAN bus has still not reached the first bit of the Intermission field When t...

Page 1132: ...values the Mailbox with the lowest number is the arbitration winner The composition of the arbitration value depends on CAN_MCR LPRIOEN bit setting 43 5 2 2 1 Local Priority disabled If CAN_MCR LPRIOE...

Page 1133: ...After the MB is transmitted and the corresponding IFLAG bit is cleared by the CPU FlexCAN enters in Freeze mode or Bus Off FlexCAN loses the bus arbitration or there is an error during the transmissio...

Page 1134: ...ror or Overload flag in the bus Low Power or Freeze mode request in Idle state Arbitration is considered pending as described below It was not possible to finish arbitration process in time C S write...

Page 1135: ...r CPU servicing read the frame received in an Mailbox is using the following procedure 1 Read the Control and Status word of that Mailbox 2 Check if the BUSY bit is deasserted indicating that the Mail...

Page 1136: ...during Freeze mode see Rx FIFO Upon receiving the Frames Available in Rx FIFO interrupt see the description of the BUF5I bit Frames available in Rx FIFO bit in the CAN_IFLAG1 register the CPU should s...

Page 1137: ...the CRC field of the frame If the received frame is a data frame with DLC field different than zero the start point is the DATA field of the frame If a matching ID is found in the FIFO table or in one...

Page 1138: ...ion structure is free to receive when any of the following conditions is satisfied The CODE field of the Mailbox is EMPTY The CODE field of the Mailbox is either FULL or OVERRUN and it has already bee...

Page 1139: ...ailbox If CAN_MCR IRMQ bit is asserted the matching winner is the Rx FIFO if it is a free to receive matched structure otherwise the matching winner is the last non free to receive matched Mailbox See...

Page 1140: ...free to receive 5 Matched in FIFO None means that the frame has not matched any filter in FIFO It is as if the FIFO didn t exist CAN_CTRL2 RFEN 0 6 Matched in FIFO NotFull means that the frame has mat...

Page 1141: ...bit is asserted then the corresponding ID bit is compared If the mask bit is negated the corresponding ID bit is a don t care Note that the Individual Mask Registers are implemented in RAM so they are...

Page 1142: ...rted Any CAN protocol error is detected Note that the pending move in is not cancelled if the module enters Freeze or Low Power mode It only stays on hold waiting for exiting Freeze and Low Power mode...

Page 1143: ...est the abortion of a pending transmission A feedback mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be aborted and was transmitted instead Two prima...

Page 1144: ...de in this case the MB is inactivated and not aborted because the transmission did not start yet One Mailbox is only aborted when the abort request is captured and kept pending until one of the previo...

Page 1145: ...ers that are part of the Rx FIFO cannot be inactivated There is no write protection on the FIFO region by FlexCAN CPU must maintain data coherency in the FIFO region when RFEN is asserted 43 5 6 3 Mai...

Page 1146: ...bit on the CODE field is asserted If the CPU reads the Control and Status word and finds out that the BUSY bit is set it should defer accessing the MB until the BUSY bit is negated Note If the BUSY bi...

Page 1147: ...ise the flag remains negated The output of the FIFO is only valid whilst the CAN_IFLAG1 BUF5I is asserted The CAN_IFLAG1 BUF6I Rx FIFO Warning is asserted when the number of unread messages within the...

Page 1148: ...43 5 7 1 Rx FIFO under DMA Operation The receive only FIFO can support DMA this feature is enabled by asserting both the CAN_MCR RFEN and CAN_MCR DMA bits The reset value of CAN_MCR DMA bit is zero to...

Page 1149: ...tion of DMA requests 43 5 7 2 Clear FIFO Operation When CAN_MCR RFEN is asserted the clear FIFO operation is a feature used to empty FIFO contents With CAN_MCR RFEN asserted the Clear FIFO occurs when...

Page 1150: ...ly enters the internal arbitration process but is considered as a normal Tx mailbox with no higher priority The data length of this frame is independent of the DLC field in the remote frame that initi...

Page 1151: ...e The Free Running Timer is not incremented during Disable Doze Stop and Freeze modes It can be reset upon a specific frame reception enabling network time synchronization See the TSYN description in...

Page 1152: ...veform A time quantum Tq is the atomic unit of time handled by the CAN engine Tq fCANCLK PRESDIV 1 The bit rate which defines the rate the CAN message is either received or transmitted is given by the...

Page 1153: ...NOTE The bit time defined by the above time segments must not be smaller than 5 time quanta For bit time calculations use an Information Processing Time IPT of 2 which is the value implemented in the...

Page 1154: ...12 4 1 4 6 13 5 1 4 7 14 6 1 4 8 15 7 1 4 9 16 8 1 4 Note The user must ensure the bit time settings are in compliance with the CAN Protocol standard ISO 11898 1 Whenever CAN bit is used as a measure...

Page 1155: ...shown in the following figures Interm Start Move Move in Window EOF bit 2 Matching Window 26 to 90 CAN bits DATA and or CRC DLC Figure 43 103 Matching and move in time windows CRC Interm Start Move bi...

Page 1156: ...e internal Arbitration process where FlexCAN finds the winner MB for transmission see Arbitration process If the Arbitration ends too early before the first bit of Intermission field then there is a c...

Page 1157: ...is reserved for Arbitration the FlexCAN may be not be able to find a winner MB in time to be transmitted with the best chance to win the bus arbitration against external nodes on the CAN bus The opti...

Page 1158: ...ufficient time to do that the following requirements must be observed The peripheral clock frequency can not be smaller than the oscillator clock frequency For 16 Mailboxes the minimum number of perip...

Page 1159: ...e mode Ignores the Rx input pin and drives the Tx pin as recessive Stops the prescaler thus halting all CAN protocol activities Grants write access to the Error Counters Register which is read only in...

Page 1160: ...Bus Interface Unit continues to operate enabling the CPU to access memory mapped registers except the Rx Mailboxes Global Mask Registers the Rx Buffer 14 Mask Register the Rx Buffer 15 Mask Register t...

Page 1161: ...n RAM may not be accessed when the module is in Doze Mode Exiting Doze mode is done in one of the following ways CPU removing the Doze mode request CPU negating the DOZE bit of the CAN_MCR Register Se...

Page 1162: ...the FlexCAN of a Stop Acknowledgement signal The CPU must only consider the FlexCAN in Stop mode when both request and acknowledgement conditions are satisfied If FlexCAN receives the global Stop mode...

Page 1163: ...f the Stop mode request the FlexCAN negates the LPMACK bit FlexCAN will then wait for 11 consecutive recessive bits to synchronize to the CAN bus As a consequence it will not receive the frame that wo...

Page 1164: ...FIFO Warning flag bit 5 becomes the Frames Available in FIFO flag and bits 4 0 are unused See the description of the Interrupt Flags 1 Register CAN_IFLAG1 for more information If both Rx FIFO and DMA...

Page 1165: ...erved words within RAM cannot be used As an example suppose FlexCAN s RAM can support up to 16 MBs CAN_CTRL2 RFFN is 0x0 and CAN_MCR MAXMB is programmed with zero The maximum number of MBs in this cas...

Page 1166: ...isabled and the FRZACK and NOTRDY bits in the CAN_MCR Register are set The Tx pin is in recessive state and FlexCAN does not initiate any transmission or reception of CAN frames Note that the Message...

Page 1167: ...itialized Other entries in each Message Buffer should be initialized as required Initialize the Rx Individual Mask Registers CAN_RXIMRn Set required interrupt mask bits in the CAN_IMASK Registers for...

Page 1168: ...Initialization application information KV4x Reference Manual Rev 2 02 2015 1168 Preliminary Freescale Semiconductor Inc...

Page 1169: ...3 SPI clocking The SPI module is clocked by the fast peripheral clock the SPI refers to it as system clock The module has an internal divider with a minimum divide is two So the SPI can run at a maxim...

Page 1170: ...O size SPI0 4 44 1 7 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module Table 44 3 SPI PCS signals SPI Module PCS Signals SPI0 SPI_PC...

Page 1171: ...ectly This is dependent on the transfer rate used for the SPI the delay between chip select assertion and presentation of data and the system interrupt latency 44 1 9 SPI Doze Mode The Doze mode for t...

Page 1172: ...SS PCSS SIN SOUT SPI Figure 44 1 SPI Block Diagram 44 2 2 Features The module supports the following features Full duplex three wire synchronous transfers Master mode Slave mode Data streaming operat...

Page 1173: ...t capability 6 peripheral chip selects PCSes expandable to 64 with external demultiplexer Deglitching support for up to 32 peripheral chip selects PCSes with external demultiplexer DMA support for add...

Page 1174: ...ed operations the SPI queues can reside in system RAM external to the module Data transfers between the queues and the module FIFOs are accomplished by a DMA controller or host CPU The following figur...

Page 1175: ...signals are controlled by the module and configured as outputs SCK SOUT PCS x 44 2 4 2 Slave Mode Slave mode allows the module to communicate with SPI bus masters In this mode the module responds to...

Page 1176: ...signal descriptions This table describes the signals on the boundary of the module that may connect off chip in alphabetical order Table 44 4 Module signal descriptions Signal Master mode Slave mode I...

Page 1177: ...a transmitted by the module Peripheral Chip Select Strobe O Used only when the peripheral chip select strobe is enabled MCR PCSSE Strobes an off module peripheral chip select demultiplexer which decod...

Page 1178: ...0C Clock and Transfer Attributes Register In Master Mode SPI_CTAR0 32 R W 7800_0000h 44 4 3 1183 4002_C00C Clock and Transfer Attributes Register In Slave Mode SPI_CTAR0_SLAVE 32 R W 7800_0000h 44 4 4...

Page 1179: ...e FIFO Registers SPI_RXFR0 32 R 0000_0000h 44 4 11 1199 4002_C080 Receive FIFO Registers SPI_RXFR1 32 R 0000_0000h 44 4 11 1199 4002_C084 Receive FIFO Registers SPI_RXFR2 32 R 0000_0000h 44 4 11 1199...

Page 1180: ...ROOE Reserved PCSIS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DOZE MDIS DIS_ TXF DIS_ RXF 0 0 SMPL_PT 0 Reserved Reserved HALT W CLR_TXF CLR_RXF Reset 0 1 0...

Page 1181: ...O Overflow Overwrite Enable In the RX FIFO overflow condition configures the module to ignore the incoming serial data or overwrite existing data If the RX FIFO is full and new data is received the da...

Page 1182: ...is bit can only be written when the MDIS bit is cleared 0 RX FIFO is enabled 1 RX FIFO is disabled 11 CLR_TXF Clear TX FIFO Flushes the TX FIFO Writing a 1 to CLR_TXF clears the TX FIFO Counter The CL...

Page 1183: ...tions Field Description 31 16 SPI_TCNT SPI Transfer Counter Counts the number of SPI transfers the module makes The SPI_TCNT field increments every time the last bit of an SPI frame is transmitted A v...

Page 1184: ...W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CTARn field descriptions Field Description 31 DBR Double Baud Rate Doubles the effective baud rate of the Serial Communications Clock SCK This field is used...

Page 1185: ...ul communication between serial devices the devices must have identical clock phase settings In Continuous SCK mode the bit value is ignored and the transfers are done as if the CPHA bit is set to 1 0...

Page 1186: ...ency of the SCK The protocol clock is divided by the prescaler value before the baud rate selection takes place See the BR field description for details on how to compute the baud rate 00 Baud Rate Pr...

Page 1187: ...e PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame In the Continuous Serial Communications Clock operation the DT value is fixed to one SCK clock period The...

Page 1188: ...ddress 4002_C000h base Ch offset 0d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved FMSZ CPOL CPHA 0 Reserved Reserved W Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Bit 15...

Page 1189: ...data to change and which edge causes data to be captured This bit is used in both master and slave mode For successful communication between serial devices the devices must have identical clock phase...

Page 1190: ...1c w1c w1c Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TXCTR TXNXTPTR RXCTR POPNXTPTR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_SR field descriptions Field Desc...

Page 1191: ...5 TFFF Transmit FIFO Fill Flag Provides a method for the module to request more entries to be added to the TX FIFO The TFFF bit is set while the TX FIFO is not full The TFFF bit can be cleared by writ...

Page 1192: ...The TXCTR is decremented every time an SPI command is executed and the SPI data is transferred to the shift register 11 8 TXNXTPTR Transmit Next Pointer Indicates which TX FIFO entry is transmitted du...

Page 1193: ...iption 31 TCF_RE Transmission Complete Request Enable Enables TCF flag in the SR to generate an interrupt request 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled 30 Reserved...

Page 1194: ...reset value to this field This field is reserved 22 Reserved Always write the reset value to this field This field is reserved 21 Reserved Always write the reset value to this field This field is res...

Page 1195: ...ode the register transfers 16 bits of data to the TX FIFO and 16 bits of command information to the CMD FIFO In Slave mode the CMD FIFO is not used and the 16 bits of command information are reserved...

Page 1196: ...11 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved 27 EOQ End Of Queue Host software uses this bit to signal to the module that the current SPI transfer is the last in a queue At the end...

Page 1197: ...ield to the TX FIFO In slave mode the CMD FIFO is not used and the 16 bits of command information in PUSHR are reserved Address 4002_C000h base 34h offset 4002_C034h Bit 31 30 29 28 27 26 25 24 23 22...

Page 1198: ...e visibility into the TX FIFO for debugging purposes Each register is an entry in the TX FIFO The registers are read only and cannot be modified Reading the TXFRx registers does not alter the state of...

Page 1199: ...ddress 4002_C000h base 7Ch offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1200: ...an extension of SR RXCTR The concatenated field RXCTR4 RXCTR indicates the number of entries in the RX FIFO This field is decremented every time the POPR is read And this field is incremented every ti...

Page 1201: ...ation in which the module operates as a basic SPI or a queued SPI The DCONF field in the Module Configuration Register MCR determines the module Configuration SPI configuration is selected when DCONF...

Page 1202: ...nd Running Both the states are independent of it s configuration The default state of the module is Stopped In the Stopped state no serial transfers are initiated in Master mode and no transfers are r...

Page 1203: ...O buffering mechanism The interrupt and DMA request conditions are described in Interrupts DMA requests The SPI configuration supports two block specific modes Master mode and Slave mode In Master mod...

Page 1204: ...from the POPR When the TX FIFO and CMD FIFO are disabled SR TFFF SR TFUF and SR TXCTR behave as if there is a one entry FIFO The contents of TXFRs SR TXNXTPTR are undefined Similarly when the RX FIFO...

Page 1205: ...Every time an entry is transferred from the TX FIFO to the shift register the TX FIFO Counter decrements by one At the end of a transfer the TCF bit in the SR is set to indicate the completion of a t...

Page 1206: ...ignored or shifted in to the shift register If the ROOE bit is set the incoming data is shifted in to the shift register If the ROOE bit is cleared the incoming data is ignored 44 5 2 5 2 Draining the...

Page 1207: ...cy used to drive this module in the device 44 5 3 2 PCS to SCK Delay tCSC The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge See Figure 44 29 for an illu...

Page 1208: ...ween negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame See Figure 44 29 for an illustration of the Delay after Transfer The PDT and DT fields in the CTARx r...

Page 1209: ...CK field in the CTAR based on the following formula P At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field in the CTAR based on the following formu...

Page 1210: ...bus slave does not control the SCK signal in Slave mode the values of CPOL and CPHA must be identical to the master device settings to ensure proper transmission In SPI Slave mode only CTAR0 is used T...

Page 1211: ...initiates the transfer by placing its first data bit on the SOUT pin and asserting the appropriate peripheral chip select signals to the slave device The slave responds by placing its first data bit o...

Page 1212: ...4 Bit 3 Bit 2 Bit 1 LSB first LSBFE 1 LSB Figure 44 30 Module transfer timing diagram MTFE 0 CPHA 1 FMSZ 8 The master initiates the transfer by asserting the PCS signal to the slave After the tCSC de...

Page 1213: ...io is below four the master changes SOUT at odd numbered SCK edge The point where the master samples the SIN is selected by the DSPI_MCR SMPL_PT field The master sample point can be delayed by one or...

Page 1214: ...represents the protocol clock frequency from which the Baud frequency fsck is derived 2n 2 DSPI samples SIN SMPL_PT 0 D0 D1 D2 Dn D0 D1 D2 Dn D0 D1 D2 Dn sys clk PCS SCK SOUT D1 D0 D2 Dn Tcsc Tvd_sl T...

Page 1215: ...owing figures show the Modified Transfer Format for CPHA 1 Only the condition where CPOL 0 is shown At the start of a transfer the DSPI asserts the PCS signal to the slave device After the PCS to SCK...

Page 1216: ...r or equal to half of the SCK period sys clk PCS SIN SCK SOUT D1 D0 D2 Dn D0 D1 D2 Dn Tcsc Tvd_sl Tsu_ms Thd_ms Tasc Slave samples SOUT Thd_sl Tsu_sl 2n 2 2n 1 8 7 6 5 4 3 2 1 DSPI samples SIN Figure...

Page 1217: ...ous Selection Format provides the flexibility to handle the following case The Continuous Selection Format is enabled for the SPI configuration by setting the CONT bit in the SPI command When the CONT...

Page 1218: ...ming diagram for two four bit transfers with CPHA 1 and CONT 1 PCS Master SIN tCSC PCS to SCK de l ay t ASC After SCK delay SCK CPOL 0 SCK CPOL 1 Master SOUT tCSC t ASC tCSC Figure 44 38 Example of co...

Page 1219: ...ty the slave is deselected for any further serial communication otherwise an underflow error occurs 44 5 5 Continuous Serial Communications Clock The module provides the option of generating a Continu...

Page 1220: ...tiating transfer PCS Master SIN SCK CPOL 0 SCK CPOL 1 Master SOUT tDT Figure 44 39 Continuous SCK Timing Diagram CONT 0 If the CONT bit in the TX FIFO entry is set PCS remains asserted between the tra...

Page 1221: ...dge of each frame defined by frame size programmed to the CTAR0 1 register Then the data from the buffer is transferred to the RXFIFO or DDR register If the SS negates before that last SCK edge the da...

Page 1222: ...E and the EOQ bit in the executing SPI command is 1 The module generates the interrupt request when the last bit of the SPI frame with EOQ bit set is transmitted 44 5 7 2 Transmit FIFO Fill Interrupt...

Page 1223: ...Drain Request is generated when the number of entries in the RX FIFO is not zero and the RFDF_RE bit in the RSER is set The RFDF_DIRS bit in the RSER selects whether a DMA request or an interrupt req...

Page 1224: ...e entered Module Disable Mode This also puts the module in STOPPED state The SR TXRXS bit is cleared to indicate STOPPED state If implemented the Clock Enable signal can stop the clock to the non memo...

Page 1225: ...ts in the DMA Controller 6 Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the RXCNT in SR or by checking RFDF in the SR after each read operation of the PO...

Page 1226: ...aud rate scaler BR in the CTARs The values calculated assume a 100 MHz protocol frequency and the double baud rate DBR bit is cleared NOTE The clock frequency mentioned above is given as an example in...

Page 1227: ...used to drive this module in the device Table 44 46 Delay values Delay prescaler values 1 3 5 7 Delay scaler values 2 20 0 ns 60 0 ns 100 0 ns 140 0 ns 4 40 0 ns 120 0 ns 200 0 ns 280 0 ns 8 80 0 ns...

Page 1228: ...with the FIFO Counter The TX FIFO is chosen for the illustration but the concepts carry over See Transmit First In First Out TX FIFO buffering mechanism Command First In First Out CMD FIFO Buffering M...

Page 1229: ...in the CMD FIFO is computed by the following equation CMD FIFO Base Base address of CMD FIFO CMDCTR CMD FIFO Counter CMDNXTPTR Command Next Pointer CMD FIFO Depth Command FIFO depth implementation sp...

Page 1230: ...PNXTPTR Pop Next Pointer RX FIFO Depth Receive FIFO depth implementation specific Initialization application information KV4x Reference Manual Rev 2 02 2015 1230 Preliminary Freescale Semiconductor In...

Page 1231: ...ting at higher baud rates up to a maximum of clock 20 with reduced bus loading The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance...

Page 1232: ...e slave address support DMA support 45 2 2 Modes of operation The I2C module s operation in various low power modes is as follows Run mode This is the basic mode of operation To conserve power in this...

Page 1233: ...re 45 1 I2C Functional block diagram 45 3 I2C signal descriptions The signal properties of I2C are shown in the table found here Table 45 1 I2C signal descriptions Signal Description I O SCL Bidirecti...

Page 1234: ...MBus Control and Status register I2C_SMB 8 R W 00h 45 4 9 1243 4006_6009 I2C Address Register 2 I2C_A2 8 R W C2h 45 4 10 1245 4006_600A I2C SCL Low Timeout Register High I2C_SLTH 8 R W 00h 45 4 11 124...

Page 1235: ...ling edge of SCL I2C clock to the changing of SDA I2C data SDA hold time I2C module clock period s mul SDA hold value The SCL start hold time is the delay from the falling edge of SDA I2C data while S...

Page 1236: ...en MST is changed from 0 to 1 a START signal is generated on the bus and master mode is selected When this bit changes from 1 to 0 a STOP signal is generated and the mode of operation changes from mas...

Page 1237: ...rrupt generated when address matching in low power mode 1 Enables the wakeup function in low power mode 0 DMAEN DMA Enable Enables or disables the DMA function 0 All DMA signalling disabled 1 DMA tran...

Page 1238: ...egisters IAAS sets before the ACK bit The CPU must check the SRW bit and set TX RX accordingly Writing the C1 register with any value clears this bit 0 Not addressed 1 Addressed as a slave 5 BUSY Bus...

Page 1239: ...or start detection interrupt In the interrupt service routine first clear the STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it and then clear the IICIF bit If this sequence i...

Page 1240: ...position bit 0 45 4 6 I2C Control Register 2 I2C_C2 Address 4006_6000h base 5h offset 4006_6005h Bit 7 6 5 4 3 2 1 0 Read GCAEN ADEXT HDRS SBRC RMEN AD 10 8 Write Reset 0 0 0 0 0 0 0 0 I2C_C2 field d...

Page 1241: ...ionality 1 The I2C module is configured for a basic transfer and the SHEN bit is set to 1 2 A transfer begins 3 The MCU signals the I2C module to enter stop mode 4 The byte currently being transferred...

Page 1242: ...sabled 1 Stop or start detection interrupt is enabled 4 STARTF I2C Bus Start Detect Flag Hardware sets this bit when the I2C bus s start status is detected The STARTF bit must be cleared by writing 1...

Page 1243: ...nitor the SHTF1 bit because the bus speed is too high to match the protocol of SMBus Address 4006_6000h base 8h offset 4006_6008h Bit 7 6 5 4 3 2 1 0 Read FACK ALERTEN SIICAEN TCKSEL SLTF SHTF1 SHTF2...

Page 1244: ...urs Software clears this bit by writing a logic 1 to it NOTE The low timeout function is disabled when the SLT register s value is 0 0 No low timeout occurs 1 Low timeout occurs 2 SHTF1 SCL High Timeo...

Page 1245: ...w Timeout Register High I2C_SLTH Address 4006_6000h base Ah offset 4006_600Ah Bit 7 6 5 4 3 2 1 0 Read SSLT 15 8 Write Reset 0 0 0 0 0 0 0 0 I2C_SLTH field descriptions Field Description SSLT 15 8 SSL...

Page 1246: ...ces connected to it must have open drain or open collector outputs A logic AND function is exercised on both lines with external pull up resistors The value of these resistors depends on the system No...

Page 1247: ...gh to low transition of SDA while SCL is high This signal denotes the beginning of a new data transfer each data transfer might contain several bytes of data and brings all slaves out of their idle st...

Page 1248: ...signaled from the receiving device by pulling SDA low at the ninth clock In summary one complete data transfer needs nine clock pulses If the slave receiver does not acknowledge the master in the nin...

Page 1249: ...se the transition from master to slave mode does not generate a STOP condition Meanwhile hardware sets a status bit to indicate the loss of arbitration 45 5 1 7 Clock synchronization Because wire AND...

Page 1250: ...a slave can drive SCL low for the required period and then release it If the slave s SCL low period is greater than the master s SCL low period the resulting SCL bus signal s low period is stretched...

Page 1251: ...286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129...

Page 1252: ...bits 11110 AD10 AD9 R W 0 A1 Slave address second byte AD 8 1 A2 Data A Data A A P After the master transmitter has sent the first byte of the 10 bit address the slave receiver sees an I2C interrupt...

Page 1253: ...process It provides a 7 bit address If the ADEXT bit is set AD 10 8 in Control Register 2 participates in the address matching process It extends the I2C primary slave address to a 10 bit address Add...

Page 1254: ...nd be able to receive a new START condition within the timeframe of TTIMEOUT MAX SMBus defines a clock low timeout TTIMEOUT of 35 ms specifies TLOW SEXT as the cumulative clock low extend time for a s...

Page 1255: ...intervals TLOW SEXT and TLOW MEXT When in master mode the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW MEXT within a byte where each byte is defined as START...

Page 1256: ...acknowledge its own address as a mechanism to detect the presence of a removable device such as a battery or docking station on the bus In addition to indicating a slave device busy condition SMBus u...

Page 1257: ...ICIF IICIE Arbitration lost ARBL IICIF IICIE I2C bus stop detection STOPF IICIF IICIE SSIE I2C bus start detection STARTF IICIF IICIE SSIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SDA low...

Page 1258: ...more masters try to control the bus at the same time the relative priority of the contending masters is determined by a data arbitration procedure The I2C module asserts the arbitration lost interrupt...

Page 1259: ...module The width of the glitch to absorb can be specified in terms of the number of half I2C module clock cycles A single Programmable Input Glitch Filter control register is provided Effectively any...

Page 1260: ...a DMA request instead DMA requests are generated by the transfer complete flag TCF If the DMAEN bit is set only the TCF initiates a DMA request All other events generate CPU interrupts NOTE Before th...

Page 1261: ...ister 1 to enable TX 6 Write Control Register 1 to enable MST master mode 7 Write Data register with the address of the target slave the LSB of this byte determines whether the communication is master...

Page 1262: ...s 1 If general call is enabled check to determine if the received address is a general call address 0x00 If the received address is a general call address the general call must be handled by user soft...

Page 1263: ...Data reg Clear IICIF Notes 1 If general call or SIICAEN is enabled check to determine if the received address is a general call address 0x00 or an SMBus device default address In either case they mus...

Page 1264: ...Initialization application information KV4x Reference Manual Rev 2 02 2015 1264 Preliminary Freescale Semiconductor Inc...

Page 1265: ...ast bus clock The maximum baud rate is 1 16 of related source clock frequency 3 UART0 contains 8 entry transmit and 8 entry receive FIFOs 4 All other UARTs contain a 1 entry transmit and receive FIFOs...

Page 1266: ...terrupt request See below for the mapping of the individual interrupt sources to the interrupt request The status interrupt combines the following interrupt sources Source UART 0 UART 1 Transmit data...

Page 1267: ...nsmitter output polarity Programmable receive input polarity Up to 16 bit break character transmission 11 bit break character detection option Independent FIFO structure for transmit and receive Two r...

Page 1268: ...rror Active edge on receive pin LIN break detect Receiver framing error detection Hardware parity generation and checking 1 16 bit time noise detection DMA interface 46 2 2 Modes of operation The UART...

Page 1269: ...resets the UART 46 2 2 3 Stop mode The UART is inactive during Stop mode for reduced power consumption The STOP instruction does not affect the UART register states but the UART module clock is disabl...

Page 1270: ...n occur at any time can deassert asynchronously to the other input signals RXD I Receive data Serial data input to receiver State meaning Whether RXD is interpreted as a 1 or 0 depends on the bit enco...

Page 1271: ...6 4 14 1287 4006_A010 UART FIFO Parameters UART0_PFIFO 8 R W See section 46 4 15 1289 4006_A011 UART FIFO Control Register UART0_CFIFO 8 R W 00h 46 4 16 1290 4006_A012 UART FIFO Status Register UART0_...

Page 1272: ..._TWFIFO 8 R W 00h 46 4 18 1292 4006_B014 UART FIFO Transmit Count UART1_TCFIFO 8 R 00h 46 4 19 1293 4006_B015 UART FIFO Receive Watermark UART1_RWFIFO 8 R W 01h 46 4 20 1293 4006_B016 UART FIFO Receiv...

Page 1273: ...ls NOTE The baud rate generator is disabled until C2 TE or C2 RE is set for the first time after reset The baud rate generator is disabled when SBR 0 Writing to BDH has no effect without writing to BD...

Page 1274: ...ormal operation 1 Loop mode where transmitter output is internally connected to receiver input The receiver input is determined by RSRC 6 UARTSWAI UART Stops in Wait Mode 0 UART clock continues to run...

Page 1275: ...starts after start bit 1 Idle character bit count starts after stop bit 1 PE Parity Enable Enables the parity function When parity is enabled parity function inserts a parity bit in the bit position...

Page 1276: ...ART transmitter TE can be used to queue an idle preamble by clearing and then setting TE 0 Transmitter off 1 Transmitter on 2 RE Receiver Enable Enables the UART receiver 0 Receiver off 1 Receiver on...

Page 1277: ...ween the two steps as long the handling of I O is not compromised but the order of operations is important for flag clearing When a flag is configured to trigger a DMA request assertion of the associa...

Page 1278: ...ore than the number indicated by RWFIFO RXWATER A dataword that is in the process of being received is not included in the count To clear RDRF read S1 when RDRF is set and then read D For more efficie...

Page 1279: ...r has a depth greater than 1 then there may be data in the receiver buffer that was received with noise 1 At least one dataword was received with noise detected since the last time the flag was cleare...

Page 1280: ...e for additional details RXEDGIF description NOTE The active edge is detected only in two wire mode and on receiving data coming from the RxD pin 0 No active edge on the receive pin has occurred 1 An...

Page 1281: ...LBKDE is set S1 RDRF S1 NF S1 FE and S1 PF are prevented from setting When LBKDE is set see Overrun operation 0 Break character detection is disabled 1 Break character is detected at length of 11 bit...

Page 1282: ...ion Setting this field reverses the polarity of the transmitted data output In NRZ format a one is represented by a mark and a zero is represented by a space for normal polarity and the opposite for i...

Page 1283: ...bit That one parity bit is loaded into the D register So for the data bits mask off the parity bit from the value you read out of this register When transmitting in 9 bit data format and using 8 bit w...

Page 1284: ...Registers 2 UARTx_MA2 These registers can be read and written at anytime The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4 MAEN...

Page 1285: ...M10 field does not affect the LIN send or detect break behavior If M10 is set then both C1 M and C1 PE must also be set See Data format for more information 0 The parity bit is the ninth bit in the se...

Page 1286: ...S LIN Break Detect DMA Select Bit Configures the LIN break detect flag S2 LBKDIF to generate interrupt or DMA requests if BDH LBKDIE is set NOTE If BDH LBKDIE is cleared and S2 LBKDIF is set the LBKDI...

Page 1287: ...rror 1 The dataword was received with a parity error Reserved This field is reserved This read only field is reserved and always has the value 0 46 4 14 UART Modem Register UARTx_MODEM The MODEM regis...

Page 1288: ...s no effect on RTS 1 When a character is placed into an empty transmitter data buffer RTS asserts one bit time before the start bit is transmitted RTS deasserts one bit time after all characters in th...

Page 1289: ...s set the built in FIFO structure for the transmit buffer is enabled The size of the FIFO structure is indicated by TXFIFOSIZE If this field is not set the transmit buffer operates as a FIFO of depth...

Page 1290: ...rds 100 Receive FIFO Buffer depth 32 datawords 101 Receive FIFO Buffer depth 64 datawords 110 Receive FIFO Buffer depth 128 datawords 111 Reserved 46 4 16 UART FIFO Control Register UARTx_CFIFO This r...

Page 1291: ...1 TXOF flag generates an interrupt to the host 0 RXUFE Receive FIFO Underflow Interrupt Enable When this field is set the RXUF flag generates an interrupt to the host 0 RXUF flag does not generate an...

Page 1292: ...TXOFE However an interrupt will be issued to the host only if CFIFO TXOFE is set This flag is cleared by writing a 1 0 No transmit buffer overflow has occurred since the last time the flag was cleare...

Page 1293: ...ions Field Description TXCOUNT Transmit Counter The value in this register indicates the number of datawords that are in the transmit FIFO buffer If a dataword is being transmitted that is in the tran...

Page 1294: ...0 0 0 UARTx_RCFIFO field descriptions Field Description RXCOUNT Receive Counter The value in this register indicates the number of datawords that are in the receive FIFO buffer If a dataword is being...

Page 1295: ...DMA Requests IRQ Requests TxD LOOP CONTROL LOOPS RSRC UART DATA REGISTER UART_D Figure 46 64 Transmitter Block Diagram 46 5 1 1 Transmitter character length The UART transmitter can accommodate either...

Page 1296: ...mit buffer structure The UART also sets a flag the transmit data register empty flag S1 TDRE and generates an interrupt or DMA request C5 TDMAS whenever the number of datawords in the transmit buffer...

Page 1297: ...Following this the transmit data out signal enters the idle state even if there is data pending in the UART transmit data buffer To ensure that all the data written in the FIFO is transmitted on the l...

Page 1298: ...ty bit Idle character length depends on C1 M C1 PE BDH SBNS and C4 M10 The preamble is a synchronizing idle character that begins the first transmission initiated after setting C2 TE If C2 TE is clear...

Page 1299: ...for details If the request to send operation is enabled when a character is placed into an empty transmitter data buffer RTS asserts one bit time before the start bit is transmitted RTS remains asser...

Page 1300: ...k Stop Break C5 data buffer write CTS_B RTS_B C1 in transmission 1 1 Cn transmit characters Figure 46 65 Transmitter RTS and CTS timing diagram Functional description KV4x Reference Manual Rev 2 02 20...

Page 1301: ...xD LOOPS RSRC From Transmitter RECEIVER SOURCE CONTROL To TxD Figure 46 66 UART receiver block diagram 46 5 2 1 Receiver character length The UART receiver can accommodate 8 9 or 10 bit data character...

Page 1302: ...n flags regarding the receive dataword can be read in ED register S1 RDRF is set if the number of resulting datawords in the receive buffer is equal to or greater than the number indicated by RWFIFO R...

Page 1303: ...fication RT3 RT5 and RT7 samples Start bit verification Noise flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful the RT clock...

Page 1304: ...and RT5 determine that the first low detected was noise and not the beginning of a start bit The RT clock is reset and the start bit search begins again The noise flag is not set because the noise oc...

Page 1305: ...time the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT RESET RT CLOCK 1 1 1 0 0 1 0 0 0 0 PERCEIVED START BIT ACTU...

Page 1306: ...of the start bit search and on the data the frame may be missed entirely or it may set the framing error flag SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT RESET RT CLOCK 1 1 1 1 0 0 START BIT LSB RT1...

Page 1307: ...E is set at the same time that received data is placed in the receive data buffer 46 5 2 6 Receiving break characters The UART recognizes a break character when a start bit is followed by eight nine o...

Page 1308: ...receiver can be programmed to automatically deassert and assert RTS RTS remains asserted until the transfer is complete even if the transmitter is disabled midway through a data transfer See Transceiv...

Page 1309: ...cur if the RT8 RT9 and RT10 samples are not all the same logical values A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8 RT9 and RT10 stop bit...

Page 1310: ...t takes the receiver 170 RT cycles 10 bit times 16 RT cycles 10 RT cycles With the misaligned character shown in the Figure 46 75 the receiver counts 170 RT cycles at the point when the count of the t...

Page 1311: ...errors is 170 176 170 100 3 53 46 5 2 9 Receiver wakeup C1 WAKE determines how the UART is brought out of the standby state to process an incoming message C1 WAKE enables either idle line wakeup or a...

Page 1312: ...Address operation is enabled i e C4 MAEN1 or C4 MAEN2 is set then received frame is transferred to receive buffer only if the comparison matches Address mark wakeup allows messages to contain idle ch...

Page 1313: ...ds fractional delays to the baud rate clock to allow fine trimming of the baud rate to match the system baud rate The transmitter is driven by the baud rate clock divided by 16 The receiver has an acq...

Page 1314: ...0 110 0 00 Table 46 76 Baud rate fine adjust BRFA Baud Rate Fractional Divisor BRFD 0 0 0 0 0 0 32 0 0 0 0 0 1 1 32 0 03125 0 0 0 1 0 2 32 0 0625 0 0 0 1 1 3 32 0 09375 0 0 1 0 0 4 32 0 125 0 0 1 0 1...

Page 1315: ...significant bit of the eight data bits can be used as an address mark to wake the receiver If the most significant bit is used in this way then it serves as an address or data indication leaving the...

Page 1316: ...character bits and a tenth internal data bit Note that if C4 M10 is set C1 PE must also be set In this case the tenth bit is the internally generated parity bit The ninth bit can either be used as an...

Page 1317: ...6 78 Eight bits of data with MSB first 46 5 4 3 2 Eight bit format with parity enabled BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT START BIT START BIT PARITY Figure 46 79 Seven bits of data wit...

Page 1318: ...T BIT 0 ADDRESS MARK Figure 46 85 Nine bits of data with LSB first and parity BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PARITY STOP BIT START BIT START BIT BIT 8 ADDRESS MARK Figure 46 86 Nine b...

Page 1319: ...nects the transmitter output to the receiver input Both the transmitter and receiver must be enabled C2 TE 1 and C2 RE 1 46 6 Reset All registers reset to a particular value are indicated in Memory ma...

Page 1320: ...1 RxD edge detect sensitivity Edge sensitivity can be software programmed to be either falling or rising The polarity of the edge sensitivity is selected using S2 RXINV To detect the falling edge S2...

Page 1321: ...ld settings required to configure each flag for DMA operation Table 46 80 DMA configuration Flag Request enable bit DMA select bit TDRE TIE 1 TDMAS 1 RDRF RIE 1 RDMAS 1 LBKDIF LBKDIE 1 LBKDDMAS 1 When...

Page 1322: ...for a data block has been put into the data buffer when TCFIFO TXCOUNT 0 all data has been transmitted or is in the process of transmission 3 S1 TC can be monitored When S1 TC asserts it indicates th...

Page 1323: ...with preambles with minimum idle line time use this sequence between messages 1 Write the last dataword of the first message to C3 T8 D 2 Wait for S1 TDRE to go high with TWFIFO TXWATER 0 indicating t...

Page 1324: ...Care should be taken to disable the SFIFO RXUF interrupt prior to clearing the OR flag and then clearing SFIFO RXUF after the OR flag has been cleared When LIN break detect LBKDE is asserted S1 OR has...

Page 1325: ...RTS RS 485 is a multiple drop communication protocol in which the UART transceiver s driver is 3 stated unless the UART is driving The RTS signal can be used by the transmitter to enable the driver o...

Page 1326: ...indicated otherwise in some cases it was possible for S1 IDLE to assert even if S1 OR was set 4 S1 OR will be set only if the data buffer FIFO does not have sufficient room Previously the data buffer...

Page 1327: ...abled or disabled by PORTA_PCR4 PFE control This reset default is to have this function disabled PTC6 and PTC7 have true open drain outputs thus when enabled as outputs an external pull resistor is re...

Page 1328: ...of operation Modes of operation Description Run The GPIO module operates normally Wait The GPIO module operates normally Stop The GPIO module is disabled Debug The GPIO module operates normally 47 2 3...

Page 1329: ...the system clock NOTE Not all pins within each port are implemented on each device See the chapter on signal multiplexing for the number of GPIO ports available in the device 47 3 Memory map and regi...

Page 1330: ...ort Set Output Register GPIOC_PSOR 32 W always reads 0 0000_0000h 47 3 2 1332 400F_F088 Port Clear Output Register GPIOC_PCOR 32 W always reads 0 0000_0000h 47 3 3 1332 400F_F08C Port Toggle Output Re...

Page 1331: ...utput pins NOTE Do not modify pin configuration registers associated with pins not available in your selected package All unbonded pins not available in your package will default to DISABLE state for...

Page 1332: ...n PDORn is set to logic 1 47 3 3 Port Clear Output Register GPIOx_PCOR This register configures whether to clear the fields of PDOR Address Base address 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21...

Page 1333: ...ilable in your selected package All unbonded pins not available in your package will default to DISABLE state for lowest power consumption Address Base address 10h offset Bit 31 30 29 28 27 26 25 24 2...

Page 1334: ...gital function and the corresponding Port Control and Interrupt module is enabled The Port Data Input registers return the synchronized pin state after any enabled digital filter in the Port Control a...

Page 1335: ...facilitate efficient bit manipulation on the general purpose outputs pin data set pin data clear and pin data toggle registers exist to allow one or more outputs within one port to be set cleared or...

Page 1336: ...Functional description KV4x Reference Manual Rev 2 02 2015 1336 Preliminary Freescale Semiconductor Inc...

Page 1337: ...rial format 48 1 1 Block diagram The following is a simplified block diagram of the JTAG Controller JTAGC block Refer to the chip specific configuration information as well as Register description for...

Page 1338: ...149 1 2001 defined test modes are supported as well as a bypass mode 48 1 3 1 Reset The JTAGC block is placed in reset when either power on reset is asserted or the TMS input is held high for enough c...

Page 1339: ...y of each test mode is explained in more detail in JTAGC block instructions 48 1 3 3 Bypass mode When no test operation is required the BYPASS instruction can be loaded to place the JTAGC block into b...

Page 1340: ...tion This section provides a detailed description of the JTAGC block registers accessible through the TAP interface including data registers and the instruction register Individual bit level descripti...

Page 1341: ...is always a logic 0 48 3 3 Device identification register The device identification JTAG ID register shown in the following figure allows the revision number part number manufacturer and design center...

Page 1342: ...onal pins Each bit of the boundary scan register represents a separate boundary scan register cell as described in the IEEE 1149 1 2001 standard and discussed in Boundary scan The size of the boundary...

Page 1343: ...troller is a synchronous state machine that interprets the sequence of logical values on the TMS pin The following figure shows the machine s states The value shown next to each state is the value of...

Page 1344: ...EXIT1 DR EXIT1 IR P AUSE DR P AUSE IR EXIT2 IR EXIT2 DR UPDA TE DR UPDA TE IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 48 4 IEEE 1149 1 2001 TAP controller finite state m...

Page 1345: ...1 2001 standard for more details All undefined opcodes are reserved Table 48 3 4 bit JTAG instructions Instruction Code 3 0 Instruction summary IDCODE 0000 Selects device identification register for...

Page 1346: ...s The SAMPLE portion of the instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cells at the output pins This s...

Page 1347: ...an register using the SAMPLE PRELOAD instruction before the selection of EXTEST EXTEST asserts the internal system reset for the MCU to force a predictable internal state while performing external bou...

Page 1348: ...The boundary scan register consists of this shift register chain and is connected between TDI and TDO when the EXTEST SAMPLE or SAMPLE PRELOAD instructions are loaded The shift register chain contain...

Page 1349: ...x Signal Multiplexing and Pin Assignments A 2 Introduction chapter changes Added 48 LQFP information A 3 Core overview chapter changes No substantial content changes A 4 Memories and Memory Interfaces...

Page 1350: ...es A 9 Debug chapter changes No substantial content changes A 10 Reset and Boot chapter changes No substantial content changes A 11 Signal Multiplexing chapter changes Updated Table Ports summary Adde...

Page 1351: ...A 14 RCM changes No substantial content changes A 15 SMC changes No substantial content changes A 16 MCM changes No substantial content changes A 17 PMC changes No substantial content changes A 18 LLW...

Page 1352: ...d note re channel priority errors Block parts Changed 16 32 bytes of register storage to a data buffer in Data path description Added note to DMA_CR CLM description re restriction on use of continuous...

Page 1353: ...9 MCG changes Updated the bitfield access of ATMF and LOCS0 in the MCG_SC register A 30 FMC changes A 31 FTFA changes Correct Flash Configuration Field Offset Address for VFYKEY command input Add FXAC...

Page 1354: ...A 38 FTM changes Added the following note to Introduction Block diagram and Memory map sections The number of channels supported can vary for each instance of the FTM module on a chip See the chip sp...

Page 1355: ...always in effect the bits in the MG field will mask the Mailbox filter bits Changed RXMGMASK has no effect to RXMGMASK has no effect the bits in the MG field will not mask the Mailbox filter bits In F...

Page 1356: ...s to RW for these bits In PUSHR register added note Always write the reset value to this field to Reserved bits Also updated bit field access to RW for these bits In Memory Map Register Definition sec...

Page 1357: ...A 47 JTAGC module changes No substantial content changes KV4x Reference Manual Rev 2 02 2015 Freescale Semiconductor Inc Preliminary 1357...

Page 1358: ...KV4x Reference Manual Rev 2 02 2015 1358 Preliminary Freescale Semiconductor Inc...

Page 1359: ...ncidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operati...

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