NXP Semiconductors freescale KV4 Series, Reference Manual

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45.4.2 I2C Frequency Divider register (I2C_F)
Address: 4006_6000h base + 1h offset = 4006_6001h
Bit 7 6 5 4 3 2 1 0
Read
MULT ICR
Write
Reset 0 0 0 0 0 0 0 0
I2C_F field descriptions
Field Description
7–6
MULT
Multiplier Factor
Defines the multiplier factor (mul). This factor is used along with the SCL divider to generate the I2C baud
rate.
00 mul = 1
01 mul = 2
10 mul = 4
11 Reserved
ICR ClockRate
Prescales the I2C module clock for bit rate selection. This field and the MULT field determine the I2C baud
rate, the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values
corresponding to each ICR setting, see
I2C divider and hold values .
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = I2C module clock speed (Hz)/(mul × SCL divider)
The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C data).
SDA hold time = I2C module clock period (s) × mul × SDA hold value
The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start
condition) to the falling edge of SCL (I2C clock).
SCL start hold time = I2C module clock period (s) × mul × SCL start hold value
The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
data) while SCL is high (stop condition).
SCL stop hold time = I2C module clock period (s) × mul × SCL stop hold value
For example, if the I2C module clock speed is 8 MHz, the following table shows the possible hold time
values with different ICR and MULT selections to achieve an I
2
C baud rate of 100 kbit/s.
MULT ICR
Hold times (μs)
SDA SCL Start SCL Stop
2h 00h 3.500 3.000 5.500
1h 07h 2.500 4.000 5.250
1h 0Bh 2.250 4.000 5.250
0h 14h 2.125 4.250 5.125
Table continues on the next page...
Chapter 45 Inter-Integrated Circuit (I2C)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1235