NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1056 / 1359

41.4.15 Test Register (ENC_TST)
This read/write register controls and sets the frequency of a quadrature signal generator.
It provides a quadrature test signal to the inputs of the quadrature decoder module. The
TEST_COUNT value is counted down to zero when the test module is enabled (TEN =
1) and the count is enabled (TCE = 1). Each count value of one represents a single
quadrature cycle interpreted as a count of one by the position counter (UPOS and LPOS)
if it is so enabled. Repeated writing of new values to TEST_COUNT can cause an extra
phase transition and therefore an extra count by the position counter. The period field
determines in IPBus clock cycles the length of each quadrature cycle phase. This register
is a factory test feature; however, it may be useful to customers' software development
and testing.
Address: 4005_5000h base + 1Ch offset = 4005_501Ch
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read TEN TCE QDN
TEST_PERIOD TEST_COUNT
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENC_TST field descriptions
Field Description
15
TEN
Test Mode Enable
This bit connects the test module to inputs of the quadrature decoder module.
0 Test module is not enabled
1 Test module is enabled
14
TCE
Test Counter Enable
This bit connects the test counter to inputs of the quadrature decoder module.
0 Test count is not enabled
1 Test count is enabled
13
QDN
Quadrature Decoder Negative Signal
When set, this bit generates a negative quadrature signal. Otherwise the signal is in a positive direction.
0 Leaves quadrature decoder signal in a positive direction
1 Generates a negative quadrature decoder signal
12–8
TEST_PERIOD
These bits hold the period of quadrature phase in IPBus clock cycles.
TEST_COUNT These bits hold the number of quadrature advances to generate.
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
1056
Preliminary
Freescale Semiconductor, Inc.