NXP Semiconductors Boundary Scan, Manual

Page: 6 / 15

Figure 4. NXP-MCUBootUtility-2.3.0 in eFuse to enable JTAG
3. Check the signals of three pins, TEST_MODE, GPIO_AD_B0_08, POR_B , according to the settings corresponding to
the
COMPLIANCE_PATTERN
part of the
BSDL
file. They should have the same status, 011, on the EVK board. Figure 5 is
compliance_patterns
part of the
BSDL
file. Figure 6 shows test mode and the
por_b
connection.
Figure 5. COMPLIANCE_PATTERN PART OF BSDL FILE
NXP Semiconductors
Hardware connection diagram
Introduction to Boundary Scan of i.MX RT Series, Rev. 1, March 2, 2021
Application Note 6 / 15