Freescale Semiconductor
17
MCU I/O PORT
Connector J1 provides access to the MC9S12DT256 I/O signals. The figures below show the
pin-out for the MCU I/O connector. Only signal XCLS is not available at connector J1.
Figure 7: Connector J1
V
AUX
1 2 PE1/IRQ*
GND 3 4 RESET*
PS1/TXD0 5 6 MODC/BKGD
PS0/RXD0 7 8 PP7/KWP7/PWM7/SCK2
PP0/KWP0/PWM0/MISO1 9 10 PAD07/AN07
PP1/KWP1/PWM1/MOSI1 11 12 PAD06/AN06
PT0/IOC0 13 14 PAD05/AN05
PT1/IOC1 15 16 PAD04/AN04
PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 17 18 PAD00/AN00
PM2/RXCAN1/RXCAN0/MISO0 19 20 PAD01/AN01
PM5/TXCN2/TXCAN0/TXCAN4/SCK0 21 22 PAD02/AN02
PM3/TXCAN1/TXCAN0/SS0* 23 24 PAD03/AN03
PA7/ADDR15/DATA15 25 26 PJ7/KWJ7/TXCAN4/SCL0
PA6/ADDR14/DATA14 27 28 PJ6/KWJ6/RXCAN4/SDA0
PA5/ADDR13/DATA13 29 30 PP2/KPP2/PWM2/SCK1
PA4/ADDR12/DATA12 31 32 PP3/KWP3/PWM3/SS1*
PA3/ADDR11/DATA11 33 34 PP4/KWP4/PWM4/MISO2
PA2/ADDR10/DATA10 35 36 PP5/KWP5/PWM5/MOSI2
PA1/ADDR9/DATA9 37 38 PS2/RXD1
PA0/ADDR8/DATA8 39 40 PS3/TXD1
PB7/ADDR7/DATA7 41 42 PE0/XIRQ*
PB6/ADDR6/DATA6 43 44 PE2/RW
PB5/ADDR5/DATA5 45 46 PE3/LSTRB*
PB4/ADDR4/DATA4 47 48 PE4/ECLK
PB3/ADDR3/DATA3 49 50 PT2/IOC2
PB2/ADDR2/DATA2 51 52 PT3/IOC3
PB1/ADDR1/DATA1 53 54 PT4/IOC4
PB0/ADDR0/DATA0 55 56 PT5/IOC5
PM1/TXCAN0/TXB 57 58 PT6/IOC6
PM0/RXCAN0/RXB 59 60 PT7/IOC7
