NuMaker-HMI-MA35D1-S1
Nov. 2, 2022
Page
69
of 99
Rev 1.01
N
UMA
K
E
R
-HMI
-M
A
3
5D1
-S1
U
S
E
R M
A
NU
A
L
Ma
k
er Nu
-m
be
d
NUC
47
2
Us
er Man
ua
l
6.1.8
Power Group 9 (RGMII1_PF) Schematic
Figure 6-8 shows the power group 9 dedicated for the RGMII1 (PF port) PHY circuit of the NuMaker-
SOM-MA35D16A81 board.
Figure 6-8 Power Group 9 (RGMII1_PF) Schematic
R42
4.7K
Title
Size
Document Number
Rev
Date:
Sheet
of
RGMII1_RTL8211F(D)I (VDDIO9)
2.2
NuMaker-SOM-MA35D16A81 (BGA312)
nuvoTon Technology Corp.
B
8
9
Tuesday, July 19, 2022
R71
0
F_VDD3V3
F_AVDD3V3
R72
0
F_AVDD1V
C124
10u
L23
FB
F_LED0
F_LED0
VSS
F_VDD3V3
VSS
VDD3V3
R46
4.7K
Internal1.8V(F_LED0,1,2=0,0,1)
F_LED1
R47
4.7K
F_VDD3V3
F_LED0
R48
4.7K
VSS
F_LED2
L22
FB
F_VDDIO
VSS
VDD1V8
C123
10u
F_AVDD1V
RTL8211FDI
VSS
VDD3V3
F_AVDD3V3
C126
0.1u
C136
0.1u
C130
0.1u
F_AVDD3V3
R50
4.7K
C128
30p
C129
0.1u
R51
1M
U5
RTL8211F(D)I-CG
MDIP0
1
MDIN0
2
AVDD10
3
MDIP1
4
MDIN1
5
MDIP2
6
MDIN2
7
AVDD10
8
MDIP3
9
MDIN3
10
AVD
D
33
11
PH
YR
ST
B
12
MDIO
14
MDC
13
T
XD
3
15
T
XD
2
16
T
XD
1
17
T
XD
0
18
T
XC
T
L
19
T
XC
20
DVDD10
21
RXD3/PHY AD0
22
RXD2/PLLOFF
23
RXD1/TXDLY
24
RXD0/RXDLY
25
RXCTL/PHY AD2
26
RXC/PHY AD1
27
DVDD_RG
28
DVDD33
29
REG_OUT
30
IN
T
B/
PM
EB
31
LED
0/
C
F
G_EXT
32
LED
1/
C
F
G_LD
O0
33
LED
2/
C
F
G_LD
O1
34
C
LKOU
T
35
XT
AL_I
N
36
XT
AL_OU
T
/EXT
_C
LK
37
AVD
D
10
38
R
SET
39
AVD
D
33
40
E_PAD
41
C137
0.1u
R45
4.7K
C134
0.1u
R53
4.7K
X4
X3225B 25MHz SMD
TXC7M-3.2X2.5MM
XIN
1
GND
2
GND
4
XOUT
3
C125
0.1u
C133
4.7u
VDD1V8
R40
4.7K
R41
4.7K
C132
0.1u
R44
4.7K
F_MDIP0
F_MDIN0
F_MDIP3
F_MDIP2
F_MDIP1
R52
4.7K
F_MDIN1
R43
4.7K
F_MDIN3
F_MDIN2
R49
2.49K 1%
C127
30p
C131
4.7u
C135
0.1u
VSS
VDD3V3
F_MDIN1
F_MDIP1
F_MDIN0
F_MDIP0
VDD1V8
F_LED1
F_MDIN3
F_MDIP3
F_MDIN2
F_MDIP2
VSS
VSS
VSS
nRESET
F_LED2
VSS
VSS
VSS
VSS
VSS
VSS
F_DVDDRG
VSS
VSS
VSS
VSS
F_VDD3V3
VSS
VSS
VSS
VSS
F_DVDDRG
VSS
F_VDD3V3
VSS
TXC
RXC
nR
ESET
RGMII1_RXCLK
R
GM
II
1_T
XD
3
R
GM
II
1_M
D
IO
RGMII1_RXD3
R
GM
II
1_M
D
C
R
GM
II
1_T
XC
T
L
R
GM
II
1_T
XD
0
RGMII1_RXCTL
R
GM
II
1_T
XD
1
R
GM
II
1_T
XD
2
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
R
GM
II
1_T
XC
LK
PHY Address 1 :3'b001
RGMII1_RXCLK
RGMII1_RXCTL
RGMII1_RXD0
RGMII1_RXD0
F_AVDD1V
F_VDD3V3
F_DVDDRG
F
_LED
2
F
_LED
1
F
_LED
0
RGMII1_RXD1
RGMII1_MDIO
PF1
PF0
RGMII1_MDC
F
_ET
H
_XO
F
_ET
H
_XI
RGMII1_RXCLK
PF5
RGMII1_TXD1
PF4
RGMII1_TXD0
PF3
RGMII1_TXCTL
PF2
RGMII1_RXD2
PF9
RGMII1_RXD1
PF8
RGMII1_RXD0
PF7
RGMII1_RXCTL
PF6
RGMII1_TXD3
PF13
RGMII1_TXD2
PF12
RGMII1_TXCLK
PF11
RGMII1_RXD3
PF10
Pull-up for add 2ns delay to TXC/RXC for data latch
C122
0.1u
VSS
F_VDDIO
Pull-up to disable PLL@ALDPS m ode
F_AVDD1V
RGMII1_RXD2
F_MDIP3
F_MDIP2
F_MDIP1
F
_AVD
D
1V
F_MDIP0
F_LED2
F_LED1
F_MDIN3
F_MDIN2
F_MDIN1
F_MDIN0
F
_I
N
T
B
nRESET
F_ETH_XI
F_ETH_XO
PF14
PF14
PF14
F_DVDDRG
RGMII_1/RMII_1/UART_1,2,10,11,13/I2C_4,5/SPI_1/I2S_0/SC_0/CAN_2/KPI/INT_0
U1L
MA35D16A887C
PF0/UART2_nCTS/UART1_RXD/RGMII0_RXD3/RGMII1_MDC/RMII1_MDC/KPI_COL0
D9
PF1/UART2_nRTS/UART1_TXD/RGMII0_TXCLK/RGMII1_MDIO/RMII1_MDIO/KPI_COL1
A8
PF2/UART2_RXD/RGMII0_TXD2/RGMII1_TXCTL/RMII1_TXEN/KPI_COL2
B8
PF3/UART2_TXD/RGMII0_TXD3/RGMII1_TXD0/RMII1_TXD0/KPI_COL3
C8
PF4/UART11_nCTS/UART10_RXD/I2S0_LRCK/SPI1_SS0/RGMII1_TXD1/RMII1_TXD1/CAN2_RXD/KPI_ROW0
D8
PF5/UART11_nRTS/UART10_TXD/I2S0_BCLK/SPI1_CLK/RGMII1_RXCLK/RMII1_REFCLK/CAN2_TXD/KPI_ROW1
A6
PF6/UART11_RXD/I2S0_DI/SPI1_MOSI/RGMII1_RXCTL/RMII1_CRSDV/I2C4_SDA/SC0_CLK/KPI_ROW2
A7
PF7/UART11_TXD/I2S0_DO/SPI1_MISO/RGMII1_RXD0/RMII1_RXD0/I2C4_SCL/SC0_DAT/KPI_ROW3
B7
PF8/UART13_RXD/I2C5_SDA/SPI0_SS0/RGMII1_RXD1/RMII1_RXD1/SC0_RST/KPI_COL4
D7
PF9/UART13_TXD/I2C5_SCL/SPI0_SS1/RGMII1_RXD2/RMII1_RXERR/SC0_PWR/KPI_COL5
C7
PF10/UART13_nCTS/I2S0_LRCK/SPI1_SS0/RGMII1_RXD3/SC0_CLK/KPI_COL6
D6
PF11/UART13_nRTS/I2S0_BCLK/SPI1_CLK/RGMII1_TXCLK/SC0_DAT/KPI_COL7
A5
PF12/I2S0_DI/SPI1_MOSI/RGMII1_TXD2/SC0_RST/KPI_ROW4
C6
PF13/I2S0_DO/SPI1_MISO/RGMII1_TXD3/SC0_PWR/KPI_ROW5
B6
PF14/EPWM2_BRAKE0/EADC0_ST/RGMII1_PPS/RMII1_PPS/SPI0_I2SMCLK/SPI1_I2SMCLK/CCAP1_SFIELD/RGMII0_PPS/RMII0_PPS/TM0/INT0/SPI1_SS1/QEI2_INDEX/I2S0_MCLK
D5
VDDIO9
E10
