N9H26
Mar 15, 2019
Page
15
of 29
Rev 1.01
NUDE
S
IG
N H
MI
-N9H
26
U
S
E
R
M
A
NUA
L
102
ADAC_HPOUT_L
LHPOUT
J2.2
103
ADAC_HPVDD33
AVDD33
GPA.10
104
URTXD
TXD
UART 0
GPA.11
105
URRXD
RXD
106
VDD
DVDD12
Core Power
107
ND[0]
CHIPCFG0
JP1
Power On Setting
108
ND[1]
109
ND[2]
Pull-low
110
ND[3]
JP2.1
GPIO
GPA.12
111
ND[4]
JP2.3
GPA.13
112
ND[5]
JP2.5
GPA.14
113
ND[6]
JP2.7
GPA 15
114
ND[7]
GPD.6
115
NBUSY1_
OV_FLAG
USB host
GPD.5
116
NBUSY0_
USBH_PWEN
J1
GPD.8
117
NWR_
JP2.4
GPIO
GPD.7
118
NRE_
JP2.2
GPE.11
119
NCLE
JP2.8
GPE.10
120
NALE
JP2.6
GPE.9
121
NCS1_
SPI0_D3
SPI 0
GPE.8
122
NCS0_
SPI0_D2
123
VDD33_1
DVDD33
I/O Power
GPD.14
124
SPI0_DI
SPI0_DI (D1)
SPI 0
GPD.13
125
SPI0_CSn
SPI0_CS0n
GPD.15
126
SPI0_DO
SPI0_DO (D0)
GPD.12
127
SPI0_CLK
SPI0_CLK
128
VSS
GND
Ground
Table 2-1 Pin Assignment for N9H26K51N
