ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 23 -
Revision 2.4
5
FUNCTIONAL DESCRIPTION
5.1
ARM
®
Cortex™-M0 core
The Cortex™-M0 processor is a multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface
and includes an NVIC component. It also has hardware debug functionality. The processor can
execute Thumb code and is compatible with other Cortex-M profile processor.
Figure 5-1 shows the functional blocks of processor.
Cortex-M0
Processor
core
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
unit
Debugger
interface
Bus matrix
Debug
Access Port
(DAP)
Debug
Cortex-M0 processor
Cortex-M0 components
Wakeup
Interrupt
Controller
(WIC)
Interrupts
Serial Wire
debug port
AHB-Lite interface
Figure 5-1 Functional Block Diagram
The implemented device provides:
•
A low gate count processor that features:
–
The ARMv6-M Thumb® instruction set.
–
Thumb-2 technology.
–
ARMv6-M compliant 24-bit SysTick timer.
–
A 32-bit hardware multiplier.
–
The system interface supports little-endian data accesses.
–
The ability to have deterministic, fixed-latency, interrupt handling.
–
Load/store-multiples that can be abandoned and restarted to facilitate rapid interrupt handling.
–
C Application Binary Interface compliant exception model.
This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that
enables the use of pure C functions as interrupt handlers.
–
Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE)
instructions, or the return from interrupt sleep-on-exit feature.
•
NVIC that features:
–
32 external interrupt inputs, each with four levels of priority.
–
Dedicated non-Maskable Interrupt (NMI) input.
–
Support for both level-sensitive and pulse-sensitive interrupt lines
–
Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.
•
Debug support
–
Four hardware breakpoints.
