CODEC Motherboard Manual Version 1.3
Page 32 of 66
April 12, 2016
CODEC Motherboard
13.11
CLKM Master Clock
Selecting this control bit will cause the NAU8822 device to use the PLL output as the input to its
Master Clock (IMCLK) Prescaler. If this is not selected, the IMCLK Prescaler will use the signal
on the external MCLK pin as its input.
13.12
BCLKSEL
This has an effect only if the NAU8822 device is the audio bus master. When the device is the
audio bus master, the internal IMCLK rate will be divided by the factor set in this panel, and this
will become the rate of the FS signal on the FS output pin.
13.13
SMPLR Sample Rate
This control value does NOT change the sampling rate in any way. The SMPLR value exists
because the digital signal processing algorithms have no information to know the actual physical
sample rate. This is determined by the external MCLK frequency. The only function of the
SMPLR value is to scale the ADC high pass filter coefficients to be compensated for the actual
sample rate of the system. If SMPLR is set correctly, then the high pass filter cutoff frequency will
be the desired value as listed in the NAU8822 Design Guide. The Equalizer cutoff frequencies
have no such compensation. The nominal Equalizer cutoff frequencies in the design guide are
for a 48kHz sample rate. For example, if the actual sample rate is 24kHz, then the Equalizer
cutoff frequencies will be one half of the values listed for 48kHz in the Design Guide.
13.14
Companding Control
Companding implements a non-linear compression/decompression of the audio signal as
explained in the NAU8822 device Design Guide. Most applications for the NAU8822 will not use
this feature.
13.15
PASSTHRU
When enabled, the pass-through mode causes data from the left and right ADC outputs to flow
directly into the digital signal processing chain for the DAC output section. In this mode, data on
the DACIN pin are ignored and replaced with data from the corresponding ADCs. ADC data
continues to be output on the ADCOUT pin.
13.16
Audio Interface Control
These controls affect how audio data are formatted and input or output on the serial digital audio
bus and are explained in the device Design Guide. The "MONO" control does not affect
formatting. This feature may be useful when only the left ADC is being used, and it is important
to guarantee that the right channel information is exactly zero.
13.17
Jack Detect Bus Switching
These controls affect various options related to the jack detection feature as detailed in the device
Design Guide. The idea of jack detection is that a logic level change can be sensed on one of the
GPIO pins, and this change will then enable/disable specified outputs and power control blocks.
